A family of standard cells for phase-locked loop (PLL) applications is presented. The applications are processed using a 1.5 μm, n-well, double-polysilicon, double-layer metal CMOS process. Applications include frequency synthesis for computer clock generation, disk drives, and pixel clock generators for computer monitors, with maximum frequencies up to 80 MHz. The synthesizers require no external components since the loop filter and oscillator are on chip with the phase frequency detector and the charge pump. Special voltage and current reference cells are discussed. Analysis of noise sources in the PLL demonstrates the need for reducing the phase noise of the system. A low phase noise is achieved through supply rejection techniques and by placing the oscillator in a high-gain feedback loop to minimize its noise contributions. Laboratory measurements of completed silicon show synthesizers with exceptionally linear gain, as well as transient responses and phase noise similar to predicted results View full abstract»

A family of standard cells for phase locked loop (PLL) applications has been developed for a 1.5 μm, N-well, double poly, double layer metal, CMOS process. Applications include frequency synthesis for computer clock generation, disk drives, and pixel clock generators for computer monitors, with maximum frequencies up to 80 MHz. The synthesizers require no external components, since the loop filter and oscillator are on-chip. A low phase noise has been achieved through supply rejection techniques and by placing the oscillator in a high-gain feedback loop to minimize its noise contributions. The period jitter has only high-frequency components and has been measured at 100 ps View full abstract»