Nonidealbattery and main memory effects on CPU speed-setting for low power
Martin, T.L.
Siewiorek, D.P.
Dept. of Electr. & Comput. Eng., Alabama Univ., Huntsville, AL, USA;
This paper appears in: Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Publication Date: Feb. 2001
Volume: 9
,
Issue: 1
On page(s):
29
- 34
ISSN: 1063-8210
Digital Object Identifier: 10.1109/92.920816
Current Version Published: 2002-08-07
Abstract
This paper explores the system-level power-performance tradeoffs of dynamically varying CPU speed. Previous work in CPU speed-setting considered only the power of the CPU and only CPUs that vary supply voltage with frequency. This work takes a broader approach, considering total system power, battery capacity, and main memory bandwidth. The results, which are up to a factor of four less than ideal, show that all three must be considered when setting the CPU speed
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