Memory latency in distributed shared-memory multiprocessors
Motlagh, B.S.
DeMara, R.F.
Dept. of Eng. Technol., Central Florida Univ., Orlando, FL, USA;
This paper appears in: Southeastcon '98. Proceedings. IEEE Publication Date: 24-26 April 1998
On page(s):
134
- 137
Meeting Date: 04/24/1998
- 04/26/1998
Location: Orlando, FL
ISBN: 0-7803-4391-3
Digital Object Identifier: 10.1109/SECON.1998.673311
Current Version Published: 2002-08-06
Abstract
Analytical models were developed and simulations of memory latency were performed for Uniform Memory Access (UMA), Non-Uniform Memory Access (NUMA), Local-Remote-Global (LRG), and Replicated Concurrent-Read (RCR) architectures for hit rates from 0.1 to 0.9 in steps of 0.1, memory access times of 10 nsec to 100 nsec, proportions of read/write access from 0.01 to 0.1, and block sizes of 8 to 64 words. The RCR architecture based on redundant inexpensive DRAM is shown to provide favourable performance over UMA and NUMA architectures for application and system parameters in the range evaluated. RCR outperforms LRG architectures when the hit rates of the processor cache exceed 80% and hit rates of replicated memory exceed 25%. Inclusion of a small replicated memory at each processor significantly reduces expected access time since all replicated memory READ access hits become independent of global traffic. For configurations of up to 32 processors, results show that latency is further reduced by distinguishing burst-mode transfers between isolated memory accesses and those which are incrementally outside the working set
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
You are not
logged in.
Guests
may access Abstract records free of charge.
Cart
