A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systems
Yuan-HaoChang
Tei-Wei Kuo
Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
This paper appears in: Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE Publication Date: 26-31 July 2009
On page(s):
858
- 863
Location: San Francisco, CA
ISSN: 0738-100X
ISBN: 978-1-6055-8497-3
Current Version Published: 2009-08-28
Abstract
Cost has been a major driving force in the development of the flash memory technology, but has also introduced serious challenges on reliability and performance for future products. In this work, we propose a commitment-based management strategy to resolve the reliability problem of many flash-memory products. A three-level address translation architecture with an adaptive block mapping mechanism is proposed to accelerate the address translation process with a limited amount of the RAM usage. Parallelism of operations over multiple chips is also explored with the considerations of the write constraints of multi-level-cell flash memory chips.
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