Reconfigurable Architecture for Network Flow Analysis
Yusuf, S.
Luk, W.
Sloman, M.
Dulay, N.
Lupu, E.C.
Brown, G.
Imperial Coll. London, London
This paper appears in: Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Publication Date: Jan. 2008
Volume: 16
,
Issue: 1
On page(s):
57
- 65
Location: San Francisco, CA, USA
ISSN: 1063-8210
Digital Object Identifier: 10.1109/TVLSI.2007.912115
Current Version Published: 2007-12-18
Abstract
This paper describes a reconfigurable architecture based on field-programmable gate-array (FPGA) technology for monitoring and analyzing network traffic at increasingly high network data rates. Our approach maps the performance-critical tasks of packet classification and flow monitoring into reconfigurable hardware, such that multiple flows can be processed in parallel. We explore the scalability of our system, showing that it can support flows at multi-gigabit rate; this is faster than most software-based solutions where acceptable data rates are typically no more than 100 million bits per second.
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