Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and Resets
Disch, S.
Schollm, C.
Inst. of Comput. Sci., Albert-Ludwigs-Univ. Freiburg
This paper appears in: Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific Publication Date: 23-26 Jan. 2007
On page(s):
938
- 943
Location: Yokohama
ISBN: 1-4244-0630-7
Digital Object Identifier: 10.1109/ASPDAC.2007.358110
Current Version Published: 2007-05-07
Abstract
Combinational equivalence checking is an essential task in circuit design. In this paper we focus on SAT based equivalence checking making use of incremental SAT techniques which are well known from their application in bounded model checking. Based on an analysis of shared circuit structures we present heuristics which try to maximize the benefit from incremental SAT solving in this application by looking for good orders in which the equivalence of different circuit outputs is checked. Moreover, we present a reset strategy for situations where the benefit from the incremental SAT approach seems to decrease. Experimental results demonstrate that our novel method outperforms traditional methods significantly.
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