An optimization technique for the design of multiple valued PLA's
Asari, K.V.
Eswaran, C.
Dept. of Electr. Eng., Indian Inst. of Technol., Madras, India;
This paper appears in: Computers, IEEE Transactions on Publication Date: Jan. 1994
Volume: 43
,
Issue: 1
On page(s):
118
- 122
ISSN: 0018-9340
Digital Object Identifier: 10.1109/12.250617
Current Version Published: 2002-08-06
Abstract
An optimization technique for the design of two types of multiple-valued PLAs is described. In a type-I PLA, the multiple-valued function is realized directly, whereas in a type-II PLA, output encoding is used to encode the binary output of the PLA. In both types, multiple function literal circuits are used for the purpose of minimization. It is shown that the proposed technique leads to a considerably reduced size of PLA when compared to the earlier techniques
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