Lee, D.-U.
Gaffar, A.A.
Cheung, R.C.C.
Mencer, O.
Luk, W.
Constantinides, G.A.
Dept. of Electr. Eng., California Univ., Los Angeles, CA
This paper appears in: Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Publication Date: Oct. 2006
Volume: 25
,
Issue: 10
On page(s):
1990
- 2000
Location: Sonoma, CA, USA
ISSN: 0278-0070
Digital Object Identifier: 10.1109/TCAD.2006.873887
Current Version Published: 2006-08-21
Abstract
An automated static approach for optimizing bit widths of fixed-point feedforward designs with guaranteed accuracy, called MiniBit, is presented. Methods to minimize both the integer and fraction parts of fixed-point signals with the aim of minimizing the circuit area are described. For range analysis, the technique in this paper identifies the number of integer bits necessary to meet range requirements. For precision analysis, a semianalytical approach with analytical error models in conjunction with adaptive simulated annealing is employed to optimize the number of fraction bits. The analytical models make it possible to guarantee overflow/underflow protection and numerical accuracy for all inputs over the user-specified input intervals. Using a stream compiler for field-programmable gate arrays (FPGAs), the approach in this paper is demonstrated with polynomial approximation, RGB-to-YCbCr conversion, matrix multiplication, B-splines, and discrete cosine transform placed and routed on a Xilinx Virtex-4 FPGA. Improvements for a given design reduce the area and the latency by up to 26% and 12%, respectively, over a design using optimum uniform fraction bit widths. Studies show that MiniBit-optimized designs are within 1% of the area produced from the integer linear programming approach
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