Cheung, R.C.C.
Telle, N.J.
Luk, W.
Cheung, P.Y.K.
Dept. of Comput., Imperial Coll. London, UK
This paper appears in: Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Publication Date: Sept. 2005
Volume: 13
,
Issue: 9
On page(s):
1048
- 1059
ISSN: 1063-8210
Digital Object Identifier: 10.1109/TVLSI.2005.857179
Current Version Published: 2005-10-31
Abstract
This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field GF(2m), using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiple m-bit serial multipliers; by changing the number of such serial multipliers, designers can obtain implementations with different tradeoffs in speed, size and level of security. A design generator has been developed which can automatically produce a customised ECC hardware design that meets user-defined requirements. To facilitate performance characterization, we have developed a parametric model for estimating the number of cycles for our generic ECC architecture. The resulting hardware implementations are among the fastest reported: for a key size of 270 bits, a point multiplication in a Xilinx XC2V6000 FPGA at 35 MHz can run over 1000 times faster than a software implementation on a Xeon computer at 2.6 GHz.
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