Reducing power with performance constraints for parallel sparse applications
Chen, G.
Malkowski, K.
Kandemir, M.
Raghavan, P.
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
This paper appears in: Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International Publication Date: 4-8 April 2005
On page(s):
8 pp.
ISBN: 0-7695-2312-9
Digital Object Identifier: 10.1109/IPDPS.2005.378
Current Version Published: 2005-04-18
Abstract
Sparse and irregular computations constitute a large fraction of applications in the data-intensive scientific domain. While every effort is made to balance the computational workload in such computations across parallel processors, achieving sustained near machine-peak performance with close-to-ideal load balanced computation-to-processor mapping is inherently difficult. As a result, most of the time, the loads assigned to parallel processors can exhibit significant variations. While there have been numerous past efforts that study this imbalance from the performance viewpoint, to our knowledge, no prior study has considered exploiting the imbalance for reducing power consumption during execution. Power consumption in large-scale clusters of workstations is becoming a critical issue as noted by several recent research papers from both industry and academia. Focusing on sparse matrix computations in which underlying parallel computations and data dependencies can be represented by trees, this paper proposes schemes that save power through voltage/frequency scaling. Our goal is to reduce overall energy consumption by scaling the voltages/frequencies of those processors that are not in the critical path; i.e., our approach is oriented towards saving power without incurring performance penalties.
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