Adya, S.N.
Yildiz, M.C.
Markov, I.L.
Villarrubia, P.G.
Parakh, P.N.
Madden, P.H.
Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA
This paper appears in: Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Publication Date: April 2004
Volume: 23
,
Issue: 4
On page(s):
472
- 487
ISSN: 0278-0070
Digital Object Identifier: 10.1109/TCAD.2004.825852
Current Version Published: 2004-03-30
Abstract
Over the last five years, the large scale integrated circuit placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved impressive empirical results. These advances have been supported by a nontrivial benchmarking infrastructure, and future achievements are set to draw on benchmarking as well. In this paper, we review motivations for benchmarking, especially for commercial electronic design automation, analyze available benchmarks, and point out major pitfalls in benchmarking. Our empirical data offers perhaps the first comprehensive evaluation of several leading large-scale placers on multiple benchmark families. We outline major outstanding problems and discuss the future of placement benchmarking. Furthermore, we attempt to extrapolate our experience to circuit layout tasks beyond placement.
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