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TOC Alert for Publication# 92 2016August 29<![CDATA[Table of contents]]>249C1C4416<![CDATA[IEEE Transactions on Very Large Scale Integration (VLSI) Systems]]>249C2C288<![CDATA[Defect- and Variation-Tolerant Logic Mapping in Nanocrossbar Using Bipartite Matching and Memetic Algorithm]]>249281328264086<![CDATA[Detector for MLC NAND Flash Memory Using Neighbor-<italic>A-Priori</italic> Information]]>a priori information of neighboring/interfering cells for mitigating the CCI effect in multilevel cell NAND flash memory are presented. The proposed schemes are referred to as the Even-A-Priori (Even-AP), the All-A-Priori (All-AP), and the All-AP-coupling-capacitance ratio (CCR) detectors. The main idea is to remove the CCI component from the interfering cells before CCI cancellation from the victim cell. Specifically, the mean CCRs along the victim cell’s vertical and diagonal directions are estimated to enable more accurate CCI cancellation. Performance analysis and simulation results show that the channel signal-to-noise ratio performance can be improved by up to 2 dB at a cell storage capacity of 1.8 bits/cell, which is significantly improved compared with some prior-art detection schemes.]]>249282728362812<![CDATA[Network-on-Chip-Enabled Multicore Platforms for Parallel Model Predictive Control]]>249283728503636<![CDATA[Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM]]>249285128602454<![CDATA[Magnetic Domain-Wall Racetrack Memory-Based Nonvolatile Logic for Low-Power Computing and Fast Run-Time-Reconfiguration]]>249286128722749<![CDATA[Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops]]>249287328863185<![CDATA[A 0.25–3.25-GHz Wideband CMOS-RF Spectrum Sensor for Narrowband Energy Detection]]> downconverter, a pair of complex filters, and a pair of envelope detectors to perform the spectrum sensing from 250 MHz to 3.25 GHz. The design makes use of the bandpass nature of the complex filter to achieve two objectives: 1) separation of upper sideband and lower sideband around the local oscillator signal and 2) resolution of smaller bands within a large detection bandwidth. The measured sensitivity is close to −45 dBm for a single tone test over a bandwidth of 40 MHz. The measured image reject ratio is close to 30 dB. The overall wideband detection bandwidth is 250 MHz, which is partitioned into 40-MHz narrowband chunks with eight such overlapping chunks.]]>249288728985105<![CDATA[A Statistical Design Approach for a Digitally Programmable Mismatch-Tolerant High-Speed Nauta Structure Differential OTA in 65-nm CMOS]]>249289929103447<![CDATA[A Process-Tolerant, Low-Voltage, Inverter-Based OTA for Continuous-Time <inline-formula> <tex-math notation="LaTeX">$Sigma $ </tex-math></inline-formula>–<inline-formula> <tex-math notation="LaTeX">$Delta $ </tex-math></inline-formula> ADC]]> –) analog-to-digital converter (ADC). The main building block of the implemented ADC is an inverter-based amplifier. This makes the resulting – ADC easier to scale to different technology nodes. A 74-dB signal-to-noise and distortion ratio is achieved, for a signal bandwidth of 64 kHz at a sampling frequency of 6.4 MHz, while consuming from a 0.8 V supply in 65-nm CMOS technology.]]>249291129172104<![CDATA[Digitally Assisted Built-In Tuning Using Hamming Distance Proportional Signatures in RF Circuits]]>249291829313119<![CDATA[Efficient Architecture for Soft-Input Soft-Output Sphere Detection With Perfect Node Enumeration]]>249293229453169<![CDATA[Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach]]>249294629593150<![CDATA[A Compact One-Pin Mode Transition Circuit for Clock Synchronization in Current-Mode- Controlled Switching Regulators]]> BiCMOS–DMOS process. The total solution occupies 0.082 mm^{2} die area. Experimental results are presented from peak-current-mode buck regulators with one-pin synchronization circuit to show the performance improvement of using the proposed design approach over a phase-locked-loop-based design.]]>249296029694388<![CDATA[A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads]]> CMOS technology and target applications with load currents in the 10-mA range. Experimental results show that the LDO achieves a PSR better than −39 dB up to 20 MHz at 1.2 V output voltage, while maintaining a 97.4% current efficiency.]]>249297029824925<![CDATA[A 10-<inline-formula> <tex-math notation="LaTeX">$mu text{s}$ </tex-math></inline-formula> Transient Recovery Time Low-EMI DC-DC Buck Converter With <inline-formula> <tex-math notation="LaTeX">$Delta $ </tex-math></inline-formula>–<inline-formula> <tex-math notation="LaTeX">$Sigma $ </tex-math></inline-formula> Modulator]]> transient recovery time and a low electromagnetic interference dc–dc buck converter with a second-order delta–sigma (– modulator. The proposed buck converter employs the techniques of oversampling, noise shaping, fast-transient path, mode selector, and second-order – modulator to achieve spur reduction and to improve transient recovery time. As a result, the noise tones of the output voltage are less than the other conventional pulsewidth modulation converters. In addition, the fast-transient path could correct output voltage immediately, and the mode selector controls the duty cycle of the converter to limit overshoot voltage and undershoot voltage. The chip was implemented using a 0.35- Taiwan Semiconductor Manufacturing Company CMOS process. The measured results show that the transient recovery time is 10 from heavy load to light load and from light load to heavy load, and the noise power spectrum demonstrates a −64-dBm peak noise when the output voltage is 2 V and the output current is 300 mA. A maximum efficiency of 89% is measured at 3 V output voltage and at 3.6 V supply voltage.]]>249298329923397<![CDATA[Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM]]>249299329971100<![CDATA[FastRead: Improving Read Performance for Multilevel-Cell Flash Memory]]>249299830021367<![CDATA[Multiplierless Unity-Gain SDF FFTs]]>249300330071284<![CDATA[Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units]]>249300830121923<![CDATA[IEEE Transactions on Very Large Scale Integration (VLSI) Systems]]>249C3C3178