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TOC Alert for Publication# 92 2014December 25<![CDATA[Table of contents]]>2212C1C4415<![CDATA[IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information]]>2212C2C2137<![CDATA[A Variation-Aware Preferential Design Approach for Memory-Based Reconfigurable Computing]]>2212244924613536<![CDATA[FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations]]>2212246224753069<![CDATA[Orchestrator: Guarding Against Voltage Emergencies in Multithreaded Applications]]>2212247624872730<![CDATA[Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I—Device–Circuit Interaction and Evaluation at Device Level]]>DD below 500 mV. For this purpose, we employed numerical TCAD simulations, as well as mixed device-circuit and lookup-table simulations using either the SENTAURUS or the Verilog-A environment. In particular, in this paper, we explore the device-circuit interaction in n- and p-type TFETs, and propose a design leading to a good tradeoff between the current leakage and transistor imbalance at ultralow V_{DD}, as required in ultralow voltage systems. Then, we systematically compare the I_{OFF}, I_{ON}, effective capacitance, OFF-state and ON-state stacking factors for TFETs, SOI, and bulk MOSFETs in a wide range of V_{DD}. These results allow us to infer preliminary indications about the amenability for an aggressive voltage scaling of TFETs compared with MOSFETs, which will be further developed in the companion paper. We also report simulation results for the sensitivity of the transistors to the variation of some key device parameters. Even these process variation results set the stage for a more thorough investigation addressed in the companion paper about the limits imposed by process variability to voltage scaling for either TFETs or MOSFETs circuits.]]>2212248824982419<![CDATA[Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II–Evaluation at Circuit Level and Design Perspectives]]>2212249925124598<![CDATA[Application-Guided Power Gating Reducing Register File Static Power]]>2212251325262632<![CDATA[Digitally Controlled Pulse Width Modulator for On-Chip Power Management]]>2212252725341361<![CDATA[Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs]]>2212253525482197<![CDATA[A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs]]>2212254925602760<![CDATA[Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits]]>2212256125702464<![CDATA[Error Correction Encoding for Tightly Coupled On-Chip Buses]]>2212257125843722<![CDATA[A Systematic Design Methodology for Low-Power NoCs]]>2212258525951745<![CDATA[Analytical Solutions for Distributed Interconnect Models—Part I: Step Input Response of Finite and Semi-Infinite Lines]]>2212259626062030<![CDATA[A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps]]>2212260726203330<![CDATA[Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator]]>2212262126281753<![CDATA[A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA]]>L) was proved to have impact on its effect. In this paper, a circuit-level power model is developed to estimate the optimal V_{L} fast for field-programmable gate array (FPGA). The model is mainly based on the path delay distribution of applications and the delay function of the integrated circuit technology. It can also count minor factors, such as path overlap, transition density, and capacitance. Experiment was conducted on a 90-nm FPGA model using MCNC benchmark. The results showed that the proposed method could generate near optimum V_{L} for most benchmarks. The best power reduction ratio is only 5.6% less than the gate-level heuristic method, which is relatively precise, but our method is ~100-10000 times faster. It implies that the dual voltage design with variable VL is a possible and promising low power method for field-programmable devices.]]>2212262926341176<![CDATA[SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration]]>2212263526484336<![CDATA[An Efficient Fully Parallel Decoder Architecture for Nonbinary LDPC Codes]]>m of values. However, the memory requirements of these decoders remain high when the field size is large. In this paper, an improved trellis-based check node processing algorithm is proposed to significantly reduce the memory requirement. The number of elements in a variable-to-check message is reduced to n_{v} (n_{v} <; n_{m}). The sorted log likelihood ratio (LLR) vector of a check-to-variable (c-to-v) message is approximated using a piecewise linear function. For each a priori message, most of the LLRs are approximated with a linear function. Two low complexity LLR generation units (LGUs) are proposed to compute LLR vectors for c-to-v messages. A fully parallel NB-LDPC decoder over GF(256) is implemented with 28-nm CMOS technology. The decoder over GF(256) achieves a throughput of 546 Mb/s and an energy efficiency of 0.178 nJ/b/iter.]]>2212264926602457<![CDATA[Fast and Flexible Hardware Support for ECC Over Multiple Standard Prime Fields]]>2212266126743736<![CDATA[A 3.1 Gb/s 8<inline-formula> <tex-math notation="LaTeX">$,times,$ </tex-math></inline-formula>8 Sorting Reduced K-Best Detector With Lattice Reduction and QR Decomposition]]>2212267526885779<![CDATA[A 2-D Interpolation-Based QRD Processor With Partial Layer Mapping for MIMO-OFDM Systems]]>2212268927003627<![CDATA[A Generic and Scalable Architecture for a Large Acoustic Model and Large Vocabulary Speech Recognition Accelerator Using Logic on Memory]]>2212270127122945<![CDATA[Addressing Partitioning Issues in Parallel Circuit Simulation]]>2212271327231053<![CDATA[A Neuromorphic Approach to Path Planning Using a Reconfigurable Neuron Array IC]]>22122724273710136<![CDATA[Incorporating Hot-Carrier Injection Effects Into Timing Analysis for Large Circuits]]>2212273827511433<![CDATA[Single-Source, Single-Destination Charge Migration in Hybrid Electrical Energy Storage Systems]]>2212275227652393<![CDATA[Utilizing Circuit Structure for Scan Chain Diagnosis]]>2212276627783879<![CDATA[A Unified Write Buffer Cache Management Scheme for Flash Memory]]>2212277927922205<![CDATA[2014 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 22]]>221227932827660<![CDATA[IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information]]>2212C3C394