<![CDATA[ Very Large Scale Integration (VLSI) Systems, IEEE Transactions on - new TOC ]]> http://ieeexplore.ieee.org TOC Alert for Publication# 92 2012 February 10 <![CDATA[Table of Contents]]> 20 2 C1 C4 145 <![CDATA[IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information]]> 20 2 C2 C2 40 <![CDATA[UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations]]> 2 in IBM 0.18-μm RF CMOS technology.]]> 20 2 197 210 2696 <![CDATA[General Parameterized Thermal Modeling for High-Performance Microprocessor Design]]> 20 2 211 224 2086 <![CDATA[Analyzing Potential Throughput Improvement of Power- and Thermal-Constrained Multicore Processors by Exploiting DVFS and PCPG]]> 20 2 225 235 1083 <![CDATA[Testable Path Selection and Grouping for Faster Than At-Speed Testing]]> 20 2 236 247 1365 <![CDATA[Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code]]> 20 2 248 256 1066 <![CDATA[AdNoC: Runtime Adaptive Network-on-Chip Architecture]]> 20 2 257 269 2848 <![CDATA[Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip]]> 2. The synthesizable implementation of the proposed switch also results in a cost-effective design, fast development time, and portability.]]> 20 2 270 283 2021 <![CDATA[Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master–Slave Flip-Flops]]> 20 2 284 295 1167 <![CDATA[Rank Metric Decoder Architectures for Random Linear Network Coding With Error Control]]> 20 2 296 309 895 <![CDATA[Energy-Aware Video Encoding for Image Quality Improvement in Battery-Operated Surveillance Camera]]> 20 2 310 318 472 <![CDATA[Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design]]> min compared to the iso-area 6T bitcell.]]> 20 2 319 332 3016 <![CDATA[Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits]]> 20 2 333 343 842 <![CDATA[Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry]]> 20 2 344 356 1842 <![CDATA[Accumulator Based 3-Weight Pattern Generation]]> 20 2 357 361 436 <![CDATA[Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme]]> 20 2 361 366 892 <![CDATA[Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm]]> 20 2 366 371 337 <![CDATA[Low-Power and Area-Efficient Carry Select Adder]]> 20 2 371 375 291 <![CDATA[A Low-Power Single-Phase Clock Multiband Flexible Divider]]> 20 2 376 380 322 <![CDATA[Design of a Tri-Modal Multi-Threshold CMOS Switch With Application to Data Retentive Power Gating]]> 20 2 380 385 292 <![CDATA[Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG]]> 253 by “xoring” with a DX generator. When implemented in the TSMC 0.18- μm 1P6M CMOS process, the new reseeding-mixing PRNG (RM-PRNG) attains the best throughput rate of 6.4 Gb/s compared with other nonlinear PRNGs. In addition, the generated random sequences pass the NIST SP 800-22 statistical tests including ratio test and U-value test.]]> 20 2 385 389 449 <![CDATA[IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors]]> 20 2 390 390 93 <![CDATA[IEEE Copyright Form]]> 20 2 391 392 1564 <![CDATA[IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information]]> 20 2 C3 C3 27