http://ieeexplore.ieee.org TOC Alert for Publication# 92 2013 May 16 21 5 C1 C4 790 21 5 C2 C2 136 21 5 793 806 1485 21 5 807 820 2255 21 5 821 833 984 21 5 834 847 1899 21 5 848 861 1836 21 5 862 874 1926 21 5 875 886 1039 21 5 887 900 2050 k input lookup table (LUT)-based field-programmable gate arrays. Approximations are used to determine the delay of the critical paths in the ECSMA. This is then used to theoretically estimate the optimal number of pipeline stages and the ideal placement of each stage in the ECSMA. This paper illustrates suitable scheduling for performing point addition and doubling in a pipelined data path of the ECSMA. Finally, detailed analyses, supported with experimental results, are provided to design the fastest scalar multiplier over generic curves. Experimental results for GF(2¹⁶³) show that, when the ECSMA is suitably pipelined, the scalar multiplication can be performed in only 9.5 μs on a Xilinx Virtex V. Notably the design has an area which is significantly smaller than other reported high-speed designs, which is due to the better LUT utilization of the underlying field primitives.]]> 21 5 901 909 550 21 5 910 920 1617 2 IIE achieves 76% attention efficiency and reduces power and processing delay of the 50-mm² image processor by up to 37% and 28%, respectively, when 96% recognition accuracy is achieved.]]> 21 5 921 933 1574 21 5 934 943 672 21 5 944 957 936 21 5 958 970 3023 21 5 971 974 528 η test vectors and the key equation solver (KES) in the HDD requires long latency and remarkable hardware. In this brief, a unified syndrome computation algorithm and the corresponding architecture are proposed. Cooperating with the KES in the reduced inversion-free Berlekamp-Messy algorithm, the reduced-complexity LCC RS decoder can speed up by 57% and the area will be reduced to 62% compared with the original design for η = 3.]]> 21 5 974 978 802 21 5 979 983 574 21 5 983 987 618 21 5 988 988 98 21 5 C3 C3 94