<![CDATA[ IEEE Transactions on Circuits and Systems II: Express Briefs - new TOC ]]>
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TOC Alert for Publication# 8920 2016September26<![CDATA[Table of Contents]]>6310C1C446<![CDATA[IEEE Transactions on Circuits and Systems—II:Express Briefs publication information]]>6310C2C240<![CDATA[A Novel 10-Bit 2.8-mW TDC Design Using SAR With Continuous Disassembly Algorithm]]>6310909913603<![CDATA[Noise Figure Optimization Tool for Millimeter-Wave Receivers at Near-<inline-formula> <tex-math notation="LaTeX">$f_{max}$</tex-math></inline-formula> Frequencies]]>$f_{max}$ frequency receiver. After choosing a suitable topology and assessing its frequency dependence, an analytical derivation is carried out and preliminary frequency constraints are found. The analytical assessment is followed by a practical example using the CMOS 65-nm technology as a reference for millimeter-wave technologies, where $f_{max}=234 text{GHz}$.]]>63109149181155<![CDATA[Compensation Method for Multistage Opamps With High Capacitive Load Using Negative Capacitance]]>$mutext{m}$ CMOS process. The measurements confirm that the opamp satisfies the design target of 1.5-MHz bandwidth at the power consumption of 75 $mutext{W}$.]]>6310919923703<![CDATA[A 10-b 200-kS/s 250-nA Self-Clocked Coarse–Fine SAR ADC]]>$mutext{m}$ CMOS technology is described. The architecture consists of a coarse and a fine SAR ADC. The 2-b coarse SAR presets the two MSB capacitive arrays of the fine SAR, thus avoiding the largest sources of dynamic power consumption. The use of two low-resolution comparators in the coarse converter enables compensating for the offset mismatches between the coarse and fine ADCs. The comparator of the fine SAR ADC obtains high sensitivity and very low power owing to a gain-enhanced dynamic preamplifier. A loop delay line generates all the phases for the SAR logic and permits three different modes of operation: on-demand, self-clocked, and clocked. In the clocked mode and at 200 kS/s, this converter achieves a 9.05-b effective number of bits (ENOB) while consuming 200 nW. The resulting figure of merit (FoM) is 1.88 fJ/conversion-level.]]>63109249281058<![CDATA[Impedance-Sensing CMOS Chip for Noninvasive Light Detection in Integrated Photonics]]>6310929933810<![CDATA[An 8-Bit Compressive Sensing ADC With 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search]]>63109349381677<![CDATA[Very Sensitive Low-Noise Active-Reset CMOS Image Sensor With In-Pixel ADC]]>*s and a detection limit of 3 electrons, achieved consuming only 6 $mutext{W}$ per pixel.]]>6310939943809<![CDATA[A Simple Nonlinear Circuit Contains an Infinite Number of Functions]]>63109449482225<![CDATA[Low-Complexity MIMO Detection: A Mixture of Basic Techniques for Near-Optimal Error Rate]]>$M$- algorithm, is proposed. Essentially, this detection method has fixed complexity and can achieve near-optimal error-rate performance with affordable complexity in many cases. Results show that, in terms of giving a good tradeoff between the implementation complexity and error rate, the proposed low-complexity detection scheme can remarkably outperform some state-of-the-art counterparts, including the conventional ML detector employing QR-decomposition and $M$- algorithm and fixed-complexity sphere decoder, and owns an error rate very close to that of the optimal one.]]>63109499531023<![CDATA[Implementation of a Near-Optimal Detector for Spatial Modulation MIMO Systems]]>$mutext{m}$ CMOS technology, and its throughput is 858 Mb/s for 8 $times$ 4 64 quadrature amplitude modulation SM-MIMO systems, where the operating frequency is 286 MHz, and the power consumption is 121.3 mW. This manifests that the proposed detector is very efficient with respect to the gate count as well as the energy consumption.]]>63109549581136<![CDATA[Resource Allocation for Heterogeneous Traffic in Complex Communication Networks]]>6310959963387<![CDATA[Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution]]>$({V}_mathrm{DD,CELL})$ collapse write assist (TVC-WA) method is widely used, but it consumes a large amount of energy. In the proposed CR-TVC-WA, the virtual cell supply and ground nodes are temporarily floated and connected to each other during the write operation. This improves the write ability and significantly reduces energy consumption. Simulation results indicate that the minimum operation voltage $({V}_mathrm{MIN})$ is approximately 660 mV when the write operation is performed at 1 GHz and the extra write energy consumption (3.8 fJ) additionally required to satisfy the target yield $(6sigma)$ is reduced by 46% compared with that in the conventional TVC-WA (7.0 fJ).]]>63109649681367<![CDATA[Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations]]>63109699731014<![CDATA[The Serial Commutator FFT]]>63109749781290<![CDATA[Recurrently Decomposable 2-D Convolvers for FPGA-Based Digital Image Processing]]>63109799831534<![CDATA[An Area-Efficient Error-Resilient Ultralow-Power Subthreshold ECG Processor]]>63109849884104<![CDATA[Affine Projection Subband Adaptive Filter With Low Computational Complexity]]>6310989993917<![CDATA[UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications]]>6310994998726<![CDATA[An Improved Signed Digit Representation Approach for Constant Vector Multiplication]]>63109991003740<![CDATA[Ultralow-Area Hysteretic Control LDO With Sub-1- <inline-formula> <tex-math notation="LaTeX">$mutext{A}$</tex-math></inline-formula> Quiescent Current]]>$mutext{m}$ CMOS technology and occupies $35 mutext{m}times 35 mutext{m}$. It consumes less than 1 $mutext{A}$ in the idle state and supplies up to 100 $mutext{A}$ at 1.8 V from an unregulated supply that varies from 1.9 to 3.3 V, making it suitable for low-power low-supply-sensitivity applications.]]>631010041008979<![CDATA[IEEE Circuits and Systems Society Information]]>6310C3C334