<![CDATA[ IEEE Transactions on Circuits and Systems II: Express Briefs - new TOC ]]>
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TOC Alert for Publication# 8920 2017July 20<![CDATA[Table of Contents]]>647C1C446<![CDATA[IEEE Transactions on Circuits and Systems—II:Express Briefs publication information]]>647C2C292<![CDATA[A Fully Integrated Multistage Cross-Coupled Voltage Multiplier With No Reversion Power Loss in a Standard CMOS Process]]>dd. As a result, such a design is compatible with the standard CMOS process without any overstress voltage. The proposed single-stage CCVD and three-stage cross-coupled voltage multiplier are implemented in 0.13-μm IBM CMOS process with maximum PE values of 88.16% and 80.2%, respectively. The maximum voltage conversion efficiency reaches 99.8% under the supply voltage of 1.2 V.]]>6477377411125<![CDATA[Bandpass Class-F Power Amplifier Based on Multifunction Hybrid Cavity–Microstrip Filter]]>6477427461676<![CDATA[Delta–Sigma Encoder for Low-Power Wireless Bio-Sensors Using Ultrawideband Impulse Radio]]>6477477511074<![CDATA[A 58-ppm/°C 40-nW BGR at Supply From 0.5 V for Energy Harvesting IoT Devices]]>2. Test results show that the minimum supply voltage is 0.5 V due to the clock bootstrap and 2 × VDD doubler. The line regulation is about 1.1 mV/V in the supply voltage range of 0.5-0.9 V. With 3-bit trimming, the temperature coefficient of 58 ppm/°C in the range of -25°C-85°C and the accuracy of 0.9% (3δ) can be achieved.]]>6477527561452<![CDATA[On Frequency Detection Capability of Full-Rate Linear and Binary Phase Detectors]]>647757761990<![CDATA[A Precision Pseudo Resistor Bias Scheme for the Design of Very Large Time Constant Filters]]>647762766710<![CDATA[Memristive Model for Synaptic Circuits]]>6477677711135<![CDATA[On Die Bit Error Rate Estimator for NAND Flash Memory]]>647772776666<![CDATA[Modeling the Impact of Phase Noise on the Performance of Crystal-Free Radios]]>647777781697<![CDATA[Immediate Neighborhood Temperature Adaptive Routing for Dynamically Throttled 3-D Networks-on-Chip]]>6477827861074<![CDATA[Accurate Estimation of CMOS Power Consumption Considering Glitches by Using Waveform Lookup]]>647787791800<![CDATA[Load Disaggregation Based on Aided Linear Integer Programming]]>647792796672<![CDATA[A 7-MHz Integrated Peak-Current-Mode Buck Regulator With a Charge-Recycling Technique]]>6477978011319<![CDATA[$H_\infty $ Relay Tracking Control of Multiagent Systems With the Assistance of a Voronoi Diagram]]>∞ relay tracking control problem of a group of agents in a monitoring region. In order to solve such a problem, we partition the monitoring region into several “tracking zones” based on a Voronoi diagram. Then, we propose a novel impulsive model to describe this relay tracking problem, and define the H_{∞} performance for this model. A relay tracking control protocol, which can guarantee the desired H_{∞} performance, is designed based on the solution of a set of matrix inequalities. The effectiveness of the proposed relay tracking control algorithm is illustrated by numerical simulations.]]>647802806482<![CDATA[Digital Event-Based Control for Nonlinear Systems Without the Limit of ISS]]>647807811233<![CDATA[$2\times\text{VDD}$ 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation]]>6478128161412<![CDATA[A Reduced-Bias Approach With a Lightweight Hard-Multiple Generator to Design a Radix-8 Modulo $2^{n} + 1$ Multiplier]]>n + 1 multiplier is the bottleneck of a wide range of applications from residue number system arithmetic to cryptography. Recently, with demand for low-power and energy-efficient designs, the radix-8 Booth recoding has been considered to derive modulo 2^{n} + 1 multipliers. This brief presents two novel methods to increase the performance and improve the efficiency of radix-8 modulo 2^{n} + 1 multipliers. The first technique is a method to significantly reduce the amount of bias terms that need to be handled. The second technique is a new hard multiple generator based on a parallel-prefix structure that computes only for odd positions; it results in a lightweight parallel-prefix adder for the computation of the triple of a number with significant area-saving and improved fan-out. The implementation results based on the TSMC 65-nm technology show improvements of at least 27% and up to 57% in the area-time^{2} product when compared with the recently proposed radix-8 multiplier.]]>647817821925<![CDATA[On Diagnosing the Aging Level of Automotive Semiconductor Devices]]>6478228261144<![CDATA[Physically Unclonable Function Using an Initial Waveform of Ring Oscillators]]>6478278311758<![CDATA[Digital Multiplierless Realization of a Calcium-Based Plasticity Model]]>6478328365228<![CDATA[Continuous Class-B/J Power Amplifier Using a Nonlinear Embedding Technique]]>6478378411150<![CDATA[A Variable Step-Size Normalized Subband Adaptive Filter With a Step-Size Scaler Against Impulsive Measurement Noise]]>6478428462038<![CDATA[Real-Time Mitigation of Short-Range Leakage in Automotive FMCW Radar Transceivers]]>647847851723<![CDATA[Blind Iterative Nonlinear Distortion Compensation Based on Thresholding]]>647852856666<![CDATA[IEEE Circuits and Systems Society Information]]>647C3C3174