http://ieeexplore.ieee.org TOC Alert for Publication# 8920 2012 February 10 59 1 C1 C1 36 59 1 C2 C2 39 59 1 1 5 745 59 1 6 10 467 LC-tank loading. Circuit functionality is confirmed with a test circuit fabricated in a standard 130-nm CMOS process. The oscillator reaches a phase noise better than -121.2 dBc/Hz at 1-MHz offset across a tuning range of 3015 to 5298 MHz while consuming a less than 10.6-mA current from a 2.8-V power supply.]]> 59 1 11 15 327 Q_L is derived from the analysis of the Butler common-base surface acoustic wave (SAW) oscillator circuit. The prototype 315-MHz Butler SAW oscillator is designed, and phase-noise results before and after adding voltage-control components are measured. The SAW resonator utilized is R315 with an unloaded quality factor Q₀ of about 1.06×10⁴. The measured results of phase noise without voltage control are -159 dBc/Hz at 10 kHz and better than -165 dBc/Hz at 100 kHz. After adding the low-voltage varactor BB155, the measured phase-noise results with different control voltages are presented. When only one varactor is added in the actual circuit, the voltage-controlled slope is 4.8 kHz/V, and the measured phase-noise results are better than -155 dBc/Hz at 10 kHz and -165 dBc/Hz at 100 kHz with different control voltages of 4, 6, and 8 V. When two varactors in series are used, the voltage-controlled slope is 9.5 kHz/V, and the measured phase-noise results are better than -155 dBc/Hz at 10 kHz and -165 dBc/Hz at 100 kHz with different control voltages of 4, 6, and 8 V. Experimental results show that the phase-noise level of the 315-MHz voltage-controlled SAW oscillator with a wide voltage-controlled range can be ameliorated based on improving Q_L.]]> 59 1 16 19 544 59 1 20 24 139 Q factor in cross-coupled LC oscillators using time-varying root locus is proposed. The extraction utilizes root computations and analytical expression of the cross-coupled-pair admittance. The methodology permits to investigate the Q-factor degradation mechanisms in large-signal LC oscillators and to compare different oscillator topologies. The obtained effective Q factor is validated through SpectreRF simulations and phase noise measurements of a voltage-controlled oscillator fabricated on a 130-nm process.]]> 59 1 25 29 544 59 1 30 34 718 59 1 35 39 755 2. Experimental results show that it can deliver a load current of 100 mA at a dropout voltage of 150 mV. It only consumes a quiescent current of 7 μA at light loads and can recover within 0.15 μs, even under the maximum load current change. Consequently, a faster and more accurate capacitorless LDO can be achieved.]]> 59 1 40 44 522 59 1 45 49 702 59 1 50 54 566 V_DD to 2V_DD suppresses the subthreshold leakage current. As compared with other reported works, the proposed bootstrapped inverter uses fewer transistors operated in the subthreshold region. Therefore, our design has shorter delay time. The Monte Carlo analysis results indicate that a sigma of delay time is only 6.3 ns under the process and temperature variations with 200-mV operation. Additionally, a test chip is fabricated in the 90-nm SPRVT low-K CMOS process. Chip measurement results demonstrate the feasibility of operating ten-stage bootstrapped inverters with a 200-fF loading of each stage at 200-mV V_DD. The test chip is able to achieve 10-MHz clock rate at 200 mV V_DD, the power consumption is 1.01 μW, and the leakage power is 107 nW.]]> 59 1 55 59 788 59 1 60 64 139 q factor. The PSNR is over 78 dB at least for 256- and 512-point window lengths. Compared with Nikolajevic and Fettweis's algorithm for complexity analysis, the results show that the proposed algorithm greatly reduces 50.21% of multiplications, 24.97% of additions, and 50% of computational cycles for 512-point MDCT and MDST. The FPGA implementation results show that the proposed design can support 7.92 sound-channel encoding and decoding for Dolby AC-3 at a sampling rate of 48 kHz while the clock rate is set to 97 MHz.]]> 59 1 65 69 242 59 1 70 70 223 59 1 71 72 1564 59 1 C3 C3 32 59 1 C4 C4 33