http://ieeexplore.ieee.org TOC Alert for Publication# 8920 2013 May 16 60 5 C1 C1 36 60 5 C2 C2 135 $hbox{mm}^{2}$ impulse-radio ultrawideband transmitter (TX) based on a ring oscillator capable of synthesizing pulses with both controlled center frequency and bandwidth using a single duty-cycling/trigger reference input. The TX embeds a single-phase charge-pump phase-locked loop (PLL), implemented with asynchronous logic, with 55 logic elements overall. The system, including radio frequency output buffers, consumes measured 30–45 pJ/pulse with a measured efficiency of $sim$47$%$ at 285 MHz center frequency and $V_{rm dd}$ in the range of 0.97–1.17 V. At 1.2V supply, the 130 nm CMOS TX tolerates $pm$ 10$%$ $V_{rm dd}$ variation, maintaining robust lock and controlled power spectral density (PSD) at 300 MHz center frequency, $-$19 dBm radiated power at 1 MHz pulse-repetition frequency, and a fractional bandwidth of 0.23. At 300 MHz, the system achieves a measured 100 ps RMS jitter, and without output buffers, the sole PLL logic occupies an active silicon area of 0.0045 $hbox{mm}^{2}$.]]> 60 5 237 241 1536 ${S}_{11}$ below $-$ 15 dB from 500 MHz to 2.5 GHz. The 1-dB received signal compression points with a blocker present at 20/80 MHz offset for low/high band are 0 and $+$2 dBm, respectively. The NF with 0-dBm blocker is 13 dB. For low band, the in-band IIP3 and IIP2 are $-$14.8 and $> 49 hbox{dBm}$, respectively, and, for high band, $-$18.2 and $> 44 hbox{dBm}$. The circuit worst case consumes 80 mW of power.]]> 60 5 242 246 274 60 5 247 251 694 $0.0229 hbox{mm}^{2}$. The maximum power consumption from a 1.2-V supply is 15.6 mW. For two 4-Gb/s pseudorandom binary sequences of $2^{7}-1$ passing through FR4 printed circuit board traces with 5-in length and 8-mil spacing, the measured peak-topeak jitter of the data is reduced by 32.22 ps by using the adaptive XTC. The measured adaptation time of the power detection loop is 63.44 $muhbox{s}$.]]> 60 5 252 256 829 60 5 257 261 747 60 5 262 266 534 60 5 267 271 117 $4 times 4$ 64-quadrature amplitude modulation (QAM) MIMO system based on our proposed architecture is designed and implemented using the 90-nm CMOS technology. The detector can achieve a maximum throughput of 2.2 Gbit/s with an area efficiency of 3.96 Mbit/s/kGE, which is more efficient than other iterative MIMO detectors.]]> 60 5 272 276 869 60 5 277 281 1085 $2^{N}$ -length discrete Hartley transform (DHT) that can be efficiently implemented on a highly modular and parallel VLSI architecture having a regular structure is presented. The DHT algorithm can be efficiently split on several parallel parts that can be executed concurrently. Moreover, the proposed algorithm is well suited for the subexpression sharing technique that can be used to significantly reduce the hardware complexity of the highly parallel VLSI implementation. Using the advantages of the proposed algorithm and the fact that we can efficiently share the multipliers with the same constant, the number of the multipliers has been significantly reduced such that the number of multipliers is very small comparing with that of the existing algorithms. Moreover, the multipliers with a constant can be efficiently implemented in VLSI.]]> 60 5 282 286 356 60 5 287 291 582 60 5 292 296 224 60 5 C3 C3 117 60 5 C4 C4 108