<![CDATA[ IEEE Transactions on Circuits and Systems II: Express Briefs - new TOC ]]>
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TOC Alert for Publication# 8920 2018March 22<![CDATA[Table of contents]]>653C1C4489<![CDATA[IEEE Transactions on Circuits and Systems - II: Express Briefs publication information]]>653C2C261<![CDATA[A 0.4-V Miniature CMOS Current Mode Instrumentation Amplifier]]>2 while consuming $11~ {mu }text{W}$ with 14 kHz gain-independent bandwidth and common mode rejection ratio (CMRR) of 76 dB. The 130-nm design exhibits input referred noise of $1.1~ {mu }text{V}_{text{RMS}}$ for a bandwidth of 0.07–150 Hz while consuming $14~ {mu }text{W}$ and CMRR of 65 dB with 100-kHz bandwidth with chip area 0.021 mm$^{{2}}$ .]]>6532612651512<![CDATA[Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement]]>6532662701447<![CDATA[Multi-Stub-Loaded Differential-Mode Planar Multiband Bandpass Filters]]>$/$ microwave differential-mode planar multiband bandpass filters (BPFs) are presented. Each symmetrical half of the proposed balanced filtering architecture is composed of the in-series cascade of $K$ $N$ -stub-loaded cells through $K-1$ inter-connection transmission-line segments to synthesize a differential-mode transfer function with $N$ $K$ th-order passbands. Additional features of this balanced multiband BPF topology are as follows: 1) generation of transmission zeros at both sides of all differential-mode passbands; 2) high common-mode power-rejection levels within the differential-mode passband ranges; 3) scalability to any number of arbitrary-order differential-mode transmission bands; and 4) lack of electromagnetic couplings in its physical structure. The theoretical foundations of the engineered balanced filter approach, along with guidelines to design the differential-mode transfer function and to attain optimum in-band common-mode power-attenuation characteristics, are expounded. Furthermore, for experimental-demonstration purposes, a third-order triple-band microstrip prototype with differential-mode passbands that are located within the range 1.4–3 GHz is manufactured and characterized.]]>6532712751167<![CDATA[A Fast-Locking All-Digital Multiplying DLL for Fractional-Ratio Dynamic Frequency Scaling]]>2 with programmable frequency ratios of ${N}$ = 1, 4, 5, 8, 10, and ${M}boldsymbol {=} 1$ , 2, 3. It operates over a frequency range of 0.7–2.0 GHz and achieves an effective peak-to-peak jitter of 10 ps at 2 GHz when ${N}$ /${M}$ = 8/2. It achieves a locking time of only 40 clock cycles and dissipates 3.3 mW at 1 GHz when ${N}$ /${M}$ = 1/1. The FMDLL employs a new harmonic lock detector to eliminate the harmonic lock problem and achieve dynamic switching of the clock frequencies and division ratios.]]>6532762801526<![CDATA[A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration]]>6532812851115<![CDATA[A Multi-Cycle Switching Technique for Efficient Ultrasonic Wireless Power Delivery]]>${R_{L}}$ ). In the proposed switching scheme, the Rx transducer is first shorted for several power carrier cycles, ${T_{p}}$ , to store the energy into the Rx ultrasonic transducer, and then is opened to deliver the energy to the load. A circuit model for this scheme has been presented and verified by simulations. In a proof-of-concept measurement setup, the proposed ultrasonic WPT link, operating at ${f_{p}=1/T_{p}= 1.02}$ MHz, achieved a large rectified voltage (${V_{L}}$ ) of 4.7 V by shorting the Rx transducer for $5{times T_{p}}$ and then delivered the energy to an ${R_{L}}$ of 100 $text{k}{Omega }$ within ${T_{p}}$ , with the switching rate of ${f_{mathbf{sw}}= 1/6T_{p}= 170}$ kHz. For the same input power, a conventional ultrasonic link with a passive full-wave rectifier achieved a small ${V_{L}}$ of 1 V.]]>6532862901982<![CDATA[An Input-Feedforward Delta-Sigma Modulator With Relaxed Timing Constraints]]>6532912951091<![CDATA[A 130 nm 165 nJ/frame Compressed-Domain Smashed-Filter-Based Mixed-Signal Classifier for “In-Sensor” Analytics in Smart Cameras]]>6532963002477<![CDATA[Capacitance Super Multiplier for Sub-Hertz Low-Pass Integrated Filters]]>6533013051065<![CDATA[Supply-Doubled Pulse-Shaping High Voltage Pulser for CMUT Arrays]]>pp from 45 V supply. Acoustic measurements are conducted connecting the pulser to a CMUT with 2 pF capacitance and 8.3 MHz center frequency. The pulse shape has been adjusted for the CMUT under test to generate maximum pressure output and the results are in good agreement with a large signal CMUT model.]]>6533063101059<![CDATA[Transient Input Impedance Modeling of Rectifiers for RF Energy Harvesting Applications]]>653311315905<![CDATA[Multiparameter Sensor Interface Circuit With Integrative Baseline/Offset Compensation by Switched-Capacitor Level Shifting/Balancing]]>$Omega$ , V: 230 V/V) and a coefficient of determination (R^{2}) over 0.998, which indicates a high conversion linearity.]]>6533163201131<![CDATA[A Generalized Lower Bound on the Bit Error Rate of DCSK Systems Over Multi-Path Rayleigh Fading Channels]]>${Q}$ -function are used to solve complex integrals of the average BER expressions. Furthermore, a theoretical framework is also provided to generalize the derived analytical expression for the multi-carrier DCSK and the quadrature chaos shift keying systems. For validation of these results, a detailed comparative study with already existing numerical simulations is also provided. In this brief, the analytically derived bound matches the simulation results with a very narrow gap. Therefore, the bound allows the prediction of the actual BER of any chaos-based transmit reference modulation system and its derivatives, with negligible gap.]]>653321325430<![CDATA[A Simplified Transistor-Based Analog Predistorter for a GaN Power Amplifier]]>6533263301081<![CDATA[Virtual Channel Optimization for Overloaded MIMO Systems]]>653331335809<![CDATA[Digitally Assisted RF-Analog Self Interference Cancellation for Wideband Full-Duplex Radios]]>6533363401269<![CDATA[Fixed-Time Disturbance Observer Design for Brunovsky Systems]]>653341345490<![CDATA[Recognition and Vulnerability Analysis of Key Nodes in Power Grid Based on Complex Network Centrality]]>653346350509<![CDATA[Non-Isolated Single-Inductor DC/DC Converter With Fully Reconfigurable Structure for Renewable Energy Applications]]>6533513551079<![CDATA[Exponential Stability Analysis and Stabilization for Continuous Time-Delay Systems With Controller Failure]]>653356360352<![CDATA[Energy-Efficient Scheme for Multiple Scan-Chains BIST Using Weight-Based Segmentation]]>653361365707<![CDATA[Efficient Fault-Tolerant Design for Parallel Matched Filters]]>653366370899<![CDATA[Secure and Lightweight Compressive Sensing Using Stream Cipher]]>6533713751814<![CDATA[A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection]]>653376380962<![CDATA[HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing]]>$4,,{times } ,, 4$ multi-functional processing elements array, where a hybrid-grained structure is proposed to combine a 32-bit data path with a 1-bit data path to accommodate multiple computing granularities in 13-Dwarfs. Aiming at the flexibility of the 13-Dwarfs calculation, a directional broadcasting scheme for multi-bank memory, a cache partitioning mechanism, and cache prefetching methods are proposed to further improve HReA performance via alleviating data and configuration bandwidth bottlenecks. The HReA is implemented on a $4.83,, {times } ,, 4.93$ mm^{2} silicon with TSMC 65-nm LP1P8M CMOS technology and can efficiently perform 27 representative kernels from the 13-Dwarfs with 297 mW under 280-MHz working frequency.]]>6533813851519<![CDATA[Properties of Chebyshev Polynomials Modulo $p^k$]]>653386390268<![CDATA[An Efficient Neural Network Model for Solving the Absolute Value Equations]]>6533913951611<![CDATA[Digital Distortion-Free PWM and Click Modulation]]>653396400451<![CDATA[Polynomial Sparse Adaptive Estimation in Distributed Networks]]>6534014051178<![CDATA[A Sub-Nyquist Sampling Algorithm for Fractional Bandlimited Signals Based on AIC]]>653406410569<![CDATA[IEEE Circuits and Systems Society Information]]>653C3C351