<![CDATA[ IEEE Transactions on Circuits and Systems II: Express Briefs - new TOC ]]>
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TOC Alert for Publication# 8920 2016July 28<![CDATA[Table of Contents]]>638C1C445<![CDATA[IEEE Transactions on Circuits and Systems—II:Express Briefs publication information]]>638C2C240<![CDATA[A Low-Distortion High-Efficiency Class-D Audio Amplifier Based on Sliding Mode Control]]>2. Postlayout simulations show that the proposed architecture achieves a total harmonic distortion of 0.002% for a $2.2 text{V}_{text{pp}}$ 1-kHz input signal. It achieves a peak efficiency of 96% and a maximum output power of 400 mW at an 8- $Omega$ differential load.]]>6387137171229<![CDATA[On the Nonconvergence of the Vector Fitting Algorithm]]>638718722315<![CDATA[A 0.67- <inline-formula> <tex-math notation="LaTeX">$mutext{W}$</tex-math></inline-formula> 177-ppm/°C All-MOS Current Reference Circuit in a 0.18- <inline-formula> <tex-math notation="LaTeX">$mutext{m}$</tex-math></inline-formula> CMOS Technology]]>$mutext{m}$ CMOS technology. The proposed circuit is an extension of the resistorless current reference circuit suggested by Oguey and Aebischer. This extension is a simple circuit arrangement that is capable of reducing the temperature coefficient (TC) of Oguey's circuit. The measurements have been done on ten prototypes in the temperature range of −40 °C to +85 °C. The measured average reference current is 92.2 nA with the average TC value of 177 ppm/°C. The measured average reduction of ≈68% has been achieved in TC value of Oguey's circuit after implementing the proposed arrangement. The operating supply voltage for the proposed circuit ranges from 1.25 to 1.8 V with the line sensitivity of 7.5%/V. The measured maximum average power dissipation of the proposed current reference circuit is 0.67 $mutext{W}$ at the supply voltage of 1.8 V.]]>6387237271059<![CDATA[Analysis and Design of Two-Port <inline-formula> <tex-math notation="LaTeX">$N$</tex-math></inline-formula>- Path Bandpass Filters With Embedded Phase Shifting]]>$N$-path switched- $RC$ circuits are a promising solution for realizing tunable high- $Q$ filters on chip. Here, a novel method of embedding phase-shifting functionality into the two-port $N$- path filter response by shifting the phase of the input and output clock sets relative to each other is introduced. Furthermore, a two-port design allows us to embed variable attenuation that can be useful in applications such as wideband self-interference cancellers and phased-array front ends, where filtering, phase shifting, and variable gain are functionally required. The effect of the embedded phase shift is analyzed with linear periodically time-variant theory and has been verified through simulations and measurement. Measurement results are presented for a two-port $N$- path filter implemented in a 65-nm CMOS 0.8–1.4-GHz highly reconfigurable self-interference canceling receiver. The two-port filter achieves 13-dB gain control and full 360° phase-shift range for the in-band transfer function.]]>638728732853<![CDATA[A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector]]>6387337371058<![CDATA[Innovative Theory on Multiband NGD Topology Based on Feedback-Loop Power Combiner]]>638738742915<![CDATA[A 0.4-V Subnanowatt 8-Bit 1-kS/s SAR ADC in 65-nm CMOS for Wireless Sensor Applications]]>2.]]>6387437471169<![CDATA[Steady-State Analysis of Switching Converters via Frequency-Domain Circuit Equivalents]]>6387487523340<![CDATA[Low-Complexity Multiternary Digit Multiplier Design in CNTFET Technology]]>unary operators of multivalued logic. The proposed structure is based on the classical Wallace multiplier and includes a novel ternary multiplexer design requiring only a small number of CNTFETs. Two ternary full-adder configurations are also proposed based on an examination of the multiplier structure. In addition, the design includes a new single-trit multiplier which requires 67% less CNTFETs compared to a recent design. HSPICE simulations reveal low power-delay product for the proposed designs for different choices of drive strength. Furthermore, the designs are comparable to prior works with respect to noise margin.]]>638753757985<![CDATA[A 40-Gb/s 2<sup>11</sup>-1 PRBS With Distributed Clocking and a Trigger Countdown Output]]>11-1 pseudo-random binary sequence (PRBS) generator with trigger synchronization output (9.77-MHz rate) is implemented using synthetic transmission lines for the clock distribution. The full-rate data sequence is sourced from a 2:1 multiplex of dual shift register outputs synchronized to a half-rate clock. Quadrature half-rate clocks generated by a dual-mode (Dynastat) divide-by-2 are distributed via the synthetic lines to optimize power–speed tradeoffs in the design. The $790times 620 mutext{m}^{2}$ PRBS designed in 130-nm SiGe BiCMOS (200/280 GHz $text{f}_{mathrm{T}}/text{fmax}$) consumes 250 mA at 2.5 V (i.e., 625 mW).]]>6387587621426<![CDATA[Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links]]>6387637671079<![CDATA[Bandwidth Enhancement of Flip-Flops Using Feedback for High-Speed Integrated Circuits]]>6387687722086<![CDATA[Analog Assisted Multichannel Digital Postcorrection for Time-Interleaved ADCs]]>6387737771764<![CDATA[Periodic Properties of Chebyshev Polynomial Sequences Over the Residue Ring <inline-formula> <tex-math notation="LaTeX">$mathbb{Z}/2^{k}mathbb{Z}$</tex-math></inline-formula>]]>$mathbb{Z}/2^{k}mathbb{Z}$. In particular, it is demonstrated that a recently proposed public-key cryptosystem based on Chebyshev polynomials over $mathbb{Z}/2^{k}mathbb{Z}$ is not secure.]]>638778782334<![CDATA[A Unified Methodology for Designing Hardware Random Number Generators Based on Any Probability Distribution]]>638783787654<![CDATA[Truncated Prediction Output Feedback Control of a Class of Lipschitz Nonlinear Systems With Input Delay]]>638788792347<![CDATA[An Area Time-Efficient Structure to Find the Approximate First Two Minima for Min-Sum-Based LDPC Decoders]]>638793797582<![CDATA[Unbiased Finite-Memory Digital Phase-Locked Loop]]>638798802700<![CDATA[Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths]]>$log_{2}N !-! 2$ to $(1/2)(log_{2}N !-! 3)$, in contrast with existing two-parallel pipelined architectures. The experimental result shows that the proposed two-parallel architecture can reduce the slice and power consumption by a factor of 30% compared with a recently published work for a 64-point CFFT. Furthermore, a systematic method is also explicated to generalize the architecture to higher level of parallelism and higher radix.]]>6388038071368<![CDATA[Diameter-Constrained Overlays With Faulty Links: Equilibrium, Stability, and Upper Bounds]]>638808812754<![CDATA[IEEE Circuits and Systems Society Information]]>638C3C334