<![CDATA[ IEEE Transactions on Circuits and Systems II: Express Briefs - new TOC ]]>
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TOC Alert for Publication# 8920 2018February 19<![CDATA[Table of contents]]>652C1C4490<![CDATA[IEEE Transactions on Circuits and Systems—II:Express Briefs publication information]]>652C2C260<![CDATA[New Models for the Calibration of Four-Channel Time-Interleaved ADCs Using Filter Banks]]>652141145801<![CDATA[A 0.032-mm<sup>2</sup> 0.15-V Three-Stage Charge-Pump Scheme Using a Differential Bootstrapped Ring-VCO for Energy-Harvesting Applications]]>$text{k} {Omega }$ load and a 0.15-V input. The chip area is 0.032 mm^{2}.]]>6521461501365<![CDATA[A High-Efficiency GaN Doherty Power Amplifier With Blended Class-EF Mode and Load-Pull Technique]]>1 of −26.6 dBc at an average output power of 39.2 dBm.]]>6521511552046<![CDATA[Bootstrapping and Resetting CMOS Starter for Thermoelectric and Photovoltaic Chargers]]>$mu$ m CMOS starter that charges a temporary 1.8-V supply quickly and reliably from slow- or fast-rising photovoltaic and thermoelectric sources. For this, a jump starter helps an LC tank oscillate to a level that allows a discharge path to output power. A resetter then continually resets the circuit until the system senses the temporary supply is ready. This way, with 1.8 V, a charging system can then charge a battery quickly before the onset of another harvesting drought. The starter does not require off-chip components because it borrows the switched inductor that the charging system already uses to charge the battery. A prototype of the starter proposed charges 120 pF to 1.8 V in 15–59 $mu$ s with 1.5%–7% efficiency from a 180 $Omega$ , 220–250-mV source.]]>6521561601324<![CDATA[Time-Domain $1/f$ Noise Analysis of a Charge-Redistribution Track-and-Hold Circuit]]>1/f sources. A design-oriented expression to compute the excess noise power due to flicker noise, as a function of the sampling rate, the intended T&H resolution, and the noise parameters, is obtained. This expression shows the dependence of the relative contribution of flicker noise over white noise, on the T&H design parameters. A simplified expression allows one to assess the relative contribution of flicker noise during an early stage of the design flow.]]>652161165613<![CDATA[Electronically Tunable Fully Integrated Fractional-Order Resonator]]>${0.35{-}mu {mathrm{ m}}}$ CMOS process and based on a second-order approximation of a fractional-order differentiator/integrator magnitude optimized in the range 10 Hz–700 Hz. An attractive benefit of the proposed scheme is its electronic tuning capability.]]>6521661701026<![CDATA[A 77-dB Dynamic Range Low-Power Variable-Gain Transimpedance Amplifier for Linear LADAR]]>${mu }text{m}$ standard CMOS technology, the receiver achieved a high gain of 106 dB with four configurable gain modes, a wide linear output swing of 1 V, an input-referred noise current of $1.52~ {rm p{A}/ sqrt {Hz}}$ , and a minimum detectable signal of 400 nA at SNR = 5, leading to a linear dynamic range of 77 dB, and the power consumption in the highest gain mode was 8 mW with a 3.3-V supply.]]>6521711751189<![CDATA[Stress Relaxed Multiple Output High-Voltage Level Shifter]]>652176180930<![CDATA[A Low-Power OFDM-Based Wake-Up Mechanism for IoE Applications]]>${mu }text{m}$ CMOS technology for wake-up signal detection and consumes 120-nW power.]]>6521811851543<![CDATA[Hardware Implementation of the Preprocessing QR-Decomposition for the Soft-Output MIMO Detection With Multiple Tree Traversals]]>et al., is a well-known soft-output multiple input multiple output detector to exploit ${M}$ parallel tree traversals to deliver data with ${M}$ times of detection throughput rate. The preprocessing QR-decomposition (QRD) of the ${M}$ -by-${M}$ channel matrix for the single tree detector is of complexity proportional to ${M^{3}}$ . However, the preprocessing QRD for the LORD needs to compute the ${M}$ permuted channel matrices that are constructed from the original ${M}$ -by-${M}$ channel matrix through the root conditioning criterion. The original LORD algorithm for this root conditioning QRD (RC-QRD) relies on the Gram-Schmidt orthogonalization and is of complexity proportional to ${M^{4}}$ for large ${M}$ . In this brief, we apply the Givens rotation and take advantage of the relationships among the ${M}$ permuted matrices to develop an RC-QRD algorithm with complexity proportional to ${M^{3}}$ . Furthermore, when ${M}$ is large, our proposed RC-QRD algorithm requires the number of real Givens rotations about 1.8 times necessary for computing a conventional matrix QRD. Also, for ${M=4}$ , our proposed RC-QRD hardware architecture requires gate count 2.1 times that required by the conventional triangular systolic array to compute a matrix QRD. Accordingly, with only about two times of complexity for the preprocessing RC-QRD, the LORD is able to perform ${M}$ tree traversals to deliver data with ${M}$ times of throughput rate.]]>652186190868<![CDATA[Turbo Trellis-Coded Differential Chaotic Modulation]]>${M}$ -ary differential chaotic shift keying (${M}$ -ary DCSK) scheme. An extrinsic information transfer chart is employed to analyze the convergence over additive white Gaussian noise channel and multipath Rayleigh channels. Simulation results show that the new scheme can obtain considerable coding gains without impairing the bandwidth efficiency in comparison with the ${M}$ -ary DCSK scheme and the trellis-coded differential chaotic modulation scheme. Moreover, compared to the direct-sequence spread-spectrum turbo trellis-coded modulation scheme, TTC-DCM has lower complexity and better robustness in the absence of channel state information over multipath Rayleigh channels. Overall, because of the merits of promising performance, high bandwidth efficiency, robustness to poor channel conditions, and an easy-to-implement property, the TTC-DCM scheme is suitable for bandlimited communication applications under poor channel conditions.]]>652191195663<![CDATA[A 5-mW 750-kb/s Noninvasive Transceiver for Around-the-Head Audio Applications]]>6521962001696<![CDATA[Automatic 3D Design for Efficiency Optimization of a Class E Power Amplifier]]>${eta }$ -optimal design has been implemented by using the proposed tool. We compare the analytical design of the class-E PA implemented in TSMC 65 nm CMOS technology, with the state space model technique here described. The new design reaches an efficiency of 87% in simulation, with an ${eta }$ increment of 12% respect the original design.]]>6522012051241<![CDATA[CRITIC-Based Node Importance Evaluation in Skeleton-Network Reconfiguration of Power Grids]]>652206210462<![CDATA[Current Ripple Recovery Modeling Technique for Voltage-Mode Control Converters]]>6522112151284<![CDATA[On Some Input–Output Dynamic Properties of Complex Networks]]>652216220289<![CDATA[Discrete-Time Positive Edge-Consensus for Undirected and Directed Nodal Networks]]>652221225260<![CDATA[A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications]]>5) achieves a throughput of 21.66 Gbps and an area efficiency of 4.77 Gbps/M-gates under the TSMC 90-nm CMOS technology. The proposed decoder reaches a throughput more than 20 Gbps for the first time among the prior NB-LDPC decoders, and the area efficiency is far beyond the state-of-the-art designs.]]>652226230713<![CDATA[A Parallel Stochastic Number Generator With Bit Permutation Networks]]>$4.32{times }$ , respectively, when compared to the existing shared LFSR-based SNG. For applications, such as edge detector, multiplier, and complex multiplication, the proposed SNG has achieved reduction in execution time and area-delay-product by up to $1000{times }$ and $9 {times }$ , respectively, as compared to others.]]>652231235862<![CDATA[A Low-Error Energy-Efficient Fixed-Width Booth Multiplier With Sign-Digit-Based Conditional Probability Estimation]]>6522362401155<![CDATA[Cluster Consensus in Networks of Agents With Weighted Cooperative–Competitive Interactions]]>652241245313<![CDATA[A Locally Active Memristor and Its Application in a Chaotic Circuit]]>v-i loci of memristor and non-volatile memory via the power-off plot of memristor. A chaotic attractor is observed with a simple nonlinear circuit that only includes three circuit elements in parallel: 1) a nonlinear locally active memristor; 2) a linear passive inductor; and 3) a linear passive capacitor. Then, we analyze the dynamical characteristics of the above circuit and show complex bifurcation behaviors.]]>652246250720<![CDATA[Iterative Graph-Based Filtering for Image Abstraction and Stylization]]>6522512551033<![CDATA[A Simplified FRI Sampling System for Pulse Streams Based on Constraint Random Modulation]]>6522562601046<![CDATA[IEEE Circuits and Systems Society Information]]>652C3C352