<![CDATA[ IEEE Transactions on Circuits and Systems II: Express Briefs - new TOC ]]>
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TOC Alert for Publication# 8920 2016December 05<![CDATA[Table of contents]]>6312C1C4505<![CDATA[IEEE Transactions on Circuits and Systems—II:Express Briefs publication information]]>6312C2C273<![CDATA[Guest Editorial]]>

Emerging technologies and low-power subsystems;]]>
631210891090212<![CDATA[The First Ever Real Bistable Memristors—Part I: Theoretical Insights on Local Fading Memory]]>6312109110951581<![CDATA[The First Ever Real Bistable Memristors—Part II: Design and Analysis of a Local Fading Memory System]]>6312109611001924<![CDATA[A Coupled Memcapacitor Emulator-Based Relaxation Oscillator]]>6312110111052522<![CDATA[A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS]]> . The proposed transmitter achieves 100–250 mV single-ended swing and exhibits the energy efficiency of 1 pJ/bit at the per-pin data rate of 10 Gb/s.]]>6312110611101369<![CDATA[Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs]]>631211111115790<![CDATA[A 28.8-MHz 23-dBm-IIP3 3.2-mW Sallen-Key Fourth-Order Filter With Out-of-Band Zeros Cancellation]]> technological node. The total area occupancy is 0.12 mm and the in-band integrated noise is .]]>6312111611201258<![CDATA[Design and Analysis of a High Bandwidth Rectifying Regulator With PWM and PFM Modes]]>6312112111251069<![CDATA[A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces]]>6312112611301367<![CDATA[Area-Efficient Scaling-Free DFT/FFT Design Using Stochastic Computing]]> , - point DFT is usually implemented in the format of fast Fourier transformation (FFT) with the complexity of . Despite this significant reduction in complexity, the hardware cost of the multiplication-intensive - point FFT is still very prohibitive, particularly for many large-scale applications that require large . This brief, for the first time, proposes high-accuracy low-complexity scaling-free stochastic DFT/FFT designs. With the use of the stochastic computing technique, the hardware complexity of the DFT/FFT designs is significantly reduced. More importantly, this brief presents the scaling-free stochastic adder and the random number generator sharing scheme, which enable a significant reduction in accuracy loss and hardware cost. Analysis results show that the proposed stochastic DFT/FFT designs achieve much better hardware performance and accuracy performance than state-of-the-art stochastic design.]]>6312113111351123<![CDATA[New Strategies in Removing Noncoherency From Signals With Large Distortion-to-Noise Ratios]]>6312113611402764<![CDATA[A Novel Integer-Bit Estimation Scheme in Digital Filters Based on Probabilistic Behavior of Signals in the Internal Nodes]]>631211411145612<![CDATA[A Fault-Tolerant Cache System of Automotive Vision Processor Complying With ISO26262]]>6312114611501421<![CDATA[A 3-Lead ECG-on-Chip with QRS Detection and Lossless Compression for Wireless Sensors]]> process, the circuit consumes 0.96 @ 2.4 V with a core area of 1.56 mm for two-channel ECG compression and QRS detection. Small size and ultralow-power consumption makes the chip suitable for usage in wearable/ambulatory ECG sensors.]]>6312115111552463<![CDATA[A Circuit Model of Human Whole Blood in a Microfluidic Dielectric Sensor]]> of sample volume. A circuit model is developed that accurately captures the characteristics of the capacitive double-layer formed due to the ionic content of blood, as well as the characteristics of the dispersion region attributed to interfacial polarization of the red blood cells. The sensor-measured permittivity of human whole blood and blood samples with hematocrit levels of 0.2, 0.4, and 0.6 show an excellent agreement to simulated data from the circuit model, with rms errors less than 2.14% and 1.17% for the real and imaginary parts of permittivity, respectively, for all samples and over the full measurement frequency range of 10 kHz–100 MHz.]]>631211561160979<![CDATA[A 6.5- $mu text{W}$ /MHz Charge Buffer With 7-fF Input Capacitance in 65-nm CMOS for Noncontact Electropotential Sensing]]> with an efficiency of 6.5 /MHz. Over-the-air measurements validate its applicability to electropotential sensing.]]>6312116111651502<![CDATA[A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC]]>631211661170930<![CDATA[A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS]]>2. Two redundant bits are implemented with error tolerance of ±12 mV for dynamic comparator offset and common-mode reference (Vcm) sensitivity. The prototype is designed and fabricated in a 90-nm CMOS with a core size of (0.0125 mm^{2}). At 250 KS/s and Nyquist rate input, it consumes 52.3 nW at 0.3-V supply with an achieved signal-to-noise-and-distortion ratio of 51.21 dB and a resulting figure of merit of 0.705 fJ/conv.-step.]]>6312117111751363<![CDATA[IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors]]>6312117611761024<![CDATA[IEEE Circuits and Systems Society Information]]>6312C3C364