<![CDATA[ IEEE Transactions on Circuits and Systems I: Regular Papers - new TOC ]]>
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TOC Alert for Publication# 8919 2018February 22<![CDATA[Table of contents]]>653C1C4189<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers publication information]]>653C2C278<![CDATA[Guest Editorial Special Issue on the 2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017)]]>6538578581378<![CDATA[Analysis and Demonstration of an IIP3 Improvement Technique for Low-Power RF Low-Noise Amplifiers]]>$mu text{m}$ CMOS technology to prove the concept. Measurement results reveal that the linearized low-power LNA has a 14.8-dB voltage gain, a 3.7-dB noise figure, and a −3.7-dBm IIP3 with a power consumption of 0.336 mW.]]>6538598692601<![CDATA[A Self-Test on Wafer Level for a MEM Gyroscope Readout Based on $Delta Sigma$ Modulation]]>$Delta Sigma$ modulation. Commonly, sensor element and readout ASIC are fabricated on separate wafers. Therefore, the ability to separately characterize the sensor element and the ASIC before packaging is desirable in order to reduce unnecessary expense. For the proposed self-test, a charge integrator with collocated detection and feedback is configured to generate an additional feedback path, which is used to operate a purely electrical $Delta Sigma$ modulator on wafer level. The self-test is performed in two steps. First, an automatic compensation controller configures the collocated force-feedback and thereby verifies its functionality. In a second step, an offset is added to the settled value of the controller to generate a negative feedback path to the input of the readout interface. The resulting purely electrical $Delta Sigma$ modulator is utilized to validate the functionality of every single circuit component of the later operated electro-mechanical $Delta Sigma$ modulator. The proposed self-test makes use of the already available hardware and therefore avoids an additional hardware overhead. Numerical simulations are performed to verify the proposed compensation controller concept as well as the self-test itself. The simulation results of the self-test are confirmed by measurements.]]>6538708803334<![CDATA[A 12-b 40-MS/s Calibration-Free SAR ADC]]>6538818903686<![CDATA[Design and Analysis of 2.4 GHz $30~mu text{W}$ CMOS LNAs for Wearable WSN Applications]]>$30~mu text{W}$ of power, operate with 0.8 V and 0.18 V and show NF of 3.3 and 5.2 dB, respectively. Using a widely accepted figure-of-merit for LNAs, the proposed circuit is almost three times better than the best previously reported sub-mW LNA.]]>6538919032620<![CDATA[A Sub-1ppm/°C Current-Mode CMOS Bandgap Reference With Piecewise Curvature Compensation]]>$beta $ -compensation technique is used to cancel the PTAT and non-PTAT spread of the output due to variation of limited $beta $ in the Bipolar Junction Transistors. Moreover, the error-correcting resistors are implemented to eliminate the first-order inaccuracy of the output. The BGR designed in $0.18~mu text{m}$ 1.8-/5-V CMOS process has a minimum simulated TC of 0.42ppm/°C over a wide temperature of −60°C to 150 °C, making it appropriate to provide reference voltage for a high-precision ADC for sensor interface.]]>6539049133669<![CDATA[PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique]]>6539149242464<![CDATA[Real-Time Depth From Focus on a Programmable Focal Plane Processor]]>6539259343034<![CDATA[A 0.4-V 0.66-fJ/Cycle Retentive True-Single-Phase-Clock 18T Flip-Flop in 28-nm Fully-Depleted SOI CMOS]]>6539359452740<![CDATA[A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions]]>6539469593553<![CDATA[On Enhancing Reliability of Weak PUFs via Intelligent Post-Silicon Accelerated Aging]]>6539609692590<![CDATA[Expected Value and Variance of the Indirect Time-of-Flight Measurement With Dead Time Afflicted Single-Photon Avalanche Diodes]]>6539709812432<![CDATA[Design of Least-Squares and Minimax Composite Filters]]>6539829911201<![CDATA[Single Underwater Image Restoration Using Adaptive Attenuation-Curve Prior]]>65399210026227<![CDATA[Anomaly Detection in Moving-Camera Video Sequences Using Principal Subspace Analysis]]>653100310152965<![CDATA[Adaptive Matrix Design for Boosting Compressed Sensing]]>Nearly Orthogonal CS) is based on a geometric constraint enforcing diversity between compressed measurements, while the second one (Maximum-Energy CS) on a heuristic screening of candidate measurements that acts as a run-time self-adapted optimization technique. Intensive simulation results show that the proposed approaches have different applications, and ensure an appreciable performance boost with respect to the state-of-the-art.]]>653101610271656<![CDATA[Design of Synthetic Central Pattern Generators Producing Desired Quadruped Gaits]]>653102810394184<![CDATA[Complex Dynamics in Arrays of Memristor Oscillators via the Flux–Charge Method]]>$N$ diffusively coupled memristor-based oscillatory/chaotic circuits, i.e., each uncoupled oscillator is a 3^{rd}–order memristor-based Chua’s circuit obtained by replacing the nonlinear resistor with an ideal flux-controlled memristor. It is shown that the state space $ mathbb {R}^{4N}$ in the voltage–current domain of the array can be decomposed in $infty ^{N}~3N$ -dimensional manifolds which are positively invariant for the nonlinear dynamics. Moreover, on each manifold the array obeys a different reduced-order dynamics in the flux-charge domain. These basic properties imply that two main types of bifurcations can occur, i.e., standard bifurcations on a fixed invariant manifold induced by changing the circuit parameters and bifurcations due to the variation of initial conditions and invariant manifold, but for fixed circuit parameters. The latter bifurcation phenomena are referred to as bifurcations without parameters. The reduced dynamics on invariant manifolds, and their analytic expressions, are the key tools for a comprehensive analysis of synchronization phenomena in the array of memristor-based Chua’s circuits. The main results are proved via a recently introduced technique for studying memristor-based circuits in the flux-charge domain.]]>653104010505149<![CDATA[Factoring Integers With a Brain-Inspired Computer]]>msieve, which implements the multiple polynomial quadratic sieve, to use the IBM Neurosynaptic System as a coprocessor for integer factorization.]]>653105110627710<![CDATA[An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults]]>653106310742671<![CDATA[Mono3D: Open Source Cell Library for Monolithic 3-D Integrated Circuits]]>653107510853934<![CDATA[A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits]]>$10^{-6}$ by about 20%, our Skew Normal-based strategy allows tracking reference micromagnetic results with an average error less than 4%. In TRNG mode, our approach also allows a better tracking of the reference 50%-switching probability contour with an error less than 1%_{abs}. However, the incorporation of the Skew Normal distribution in our Verilog-A model results in an increase of the CPU time by 50% on average as compared with the use of the built-in statistical functions.]]>653108610952560<![CDATA[A 5 pJ/pulse at 1-Gpps Pulsed Transmitter Based on Asynchronous Logic Master–Slave PLL Synthesis]]>2. To generate timing references and packets for high data rate recording devices, the synthesizer core feeds also a logic interface operating at 250 MHz with four 1.2–3.3 V external parallel channels. From reset time, the master–slave PLL combination achieves locking in a measured time of 450 ns, settling is resolved in $sim 4~mu text{s}$ , and the output pulses across the antenna load are generated with a 3.42 ps RMS jitter standard deviation. The obtained phase noise of a continuous OOK stream at 1 and 4 GHz, 1 MHz offset, is −103 and −93 dBc/Hz, respectively.]]>653109611095967<![CDATA[A Sub-mW Integrating Mixer SAR Spectrum Sensor for Portable Cognitive Radio Applications]]>$0.13mu {text{m}}$ CMOS process. The measured results indicate an average dynamic range of 27.9–25.7 dB over a frequency range of 0.05–1.25 GHz, while consuming 0.88 mW from 1.1/1.2 V supplies.]]>653111011192949<![CDATA[VLSI Designs for Joint Channel Estimation and Data Detection in Large SIMO Wireless Systems]]>653112011322334<![CDATA[A Cartesian Error Feedback Architecture]]>653113311422565<![CDATA[High-Efficiency Charge Pumps for Low-Power On-Chip Applications]]>$0.13~mu text{m}$ standard CMOS technology show that for an input supply voltage of 1.2 V, the proposed charge pump circuit reaches a power efficiency of 58.72% with an output voltage of 7.45 V, when delivering 5-mA load current, and is able to maintain a power efficiency of around 50% and an output voltage of over 5 V as the load current increases to 10 mA. Compared with the other charge pump circuits, the simulation results demonstrate better performance of proposed charge pump circuits in terms of both voltage pumping gain and power efficiency.]]>653114311532501<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors]]>6531154115453<![CDATA[IEEE Open Access Publishing]]>653115511551308<![CDATA[Introducing IEEE Collabratec]]>653115611562110<![CDATA[IEEE Circuits and Systems Society Information]]>653C3C3105