<![CDATA[ IEEE Transactions on Circuits and Systems I: Regular Papers - new TOC ]]>
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TOC Alert for Publication# 8919 2016June 23<![CDATA[Table of contents]]>634C1C441<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers publication information]]>634C2C239<![CDATA[A 0.6-V 10-bit 200-kS/s Fully Differential SAR ADC With Incremental Converting Algorithm for Energy Efficient Applications]]>6344494582002<![CDATA[Iterative Gain Enhancement in an Algorithmic ADC]]>2 in 0.25-μm CMOS and dissipates 16.2 mW. Iterative gain enhancement increases the SNDR from 44.6 dB to 78.5 dB and the SFDR from 45.9 dB to 96.2 dB. Reducing the number of gain-enhancement iterations for the LSBs increases the conversion rate from 3.57 MS/s to 4.65 MS/s with only minor performance degradation.]]>6344594694023<![CDATA[General Top/Bottom-Plate Charge Recycling Technique for Integrated Switched Capacitor DC-DC Converters]]>6344704812303<![CDATA[A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling]]>31-1 PRBS pattern satisfying BER <; 10^{-12}. The power efficiency was 2.4 mW/Gb/s at 6.5 Gb/s.]]>6344824932773<![CDATA[Derivation of the Most Energy-Efficient Source Functions by Using Calculus of Variations]]>6344945021133<![CDATA[A Study on the Programming Structures for RRAM-Based FPGA Architectures]]>LRS is smaller than the equivalent resistance of a transmission gate. Efficient programming structures for RRAMs should provide high current density with a small area footprint, to obtain a low RLRS. In this paper, we first examine the efficiency of the widely-used 2Transistor/1RRAM (2T1R) programming structure and identify four major limitations of the 2T1R structure. To overcome these limitations, we propose a 2Transmission-Gates/1RRAM (2TG1R) and a 4Transistor/ 1RRAM (4T1R) programming structures. We perform both theoretical analysis and electrical simulations on the evaluated programming structures. 4T1R programming structure is the best in terms of current density with 1.4 x and 1.1 x as compared to 2T1R and 2TG1R counterparts, respectively. We also investigate the effect of boosting the programming voltage V_{prog} of the programming structures. Experimental results show that boosting V_{prog} for all the programming structures improves driving current of the evaluated programming structures by 3 x and area efficiency by 1.7 x on average.]]>6345035163722<![CDATA[The Phase Characteristics for the Stability of 2-D Nonsymmetric Half-Plane Digital Allpass Filters]]>6345175281613<![CDATA[Analysis and Design of a Multi-Core Oscillator for Ultra-Low Phase Noise]]>6345295392669<![CDATA[Power-Performance Tradeoff Analysis of CML-Based High-Speed Transmitter Designs Using Circuit-Level Optimization]]>6345405504673<![CDATA[Design and Qualitative Robustness Analysis of an DOBC Approach for DC-DC Buck Converters With Unmatched Circuit Parameter Perturbations]]>6345515603115<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors]]>63456156136<![CDATA[IEEE Access]]>634562562457<![CDATA[Introducing IEEE Collabratec]]>634563563542<![CDATA[Open Access]]>634564564409<![CDATA[IEEE Circuits and Systems Society Information]]>634C3C334