<![CDATA[ IEEE Transactions on Circuits and Systems I: Regular Papers - new TOC ]]>
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TOC Alert for Publication# 8919 2017July 27<![CDATA[Table of contents]]>648C1C4168<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers publication information]]>648C2C2119<![CDATA[Analysis of Chopped Integrators, and Its Application to Continuous-Time Delta-Sigma Modulator Design]]>$\Delta \!\Sigma $ ) converter. Unlike an amplifier, the integrator in a continuous-time delta-sigma modulator is subject to out-of-band signals that are several orders of magnitude higher than the (desired) in-band component. This necessitates a careful analysis of frequency translation effects in a chopped integrator. This paper treats the chopped integrator as a linear periodically time-varying system, and exploits the adjoint (inter-reciprocal) network concept to simplify the analysis of aliasing effects in such an integrator. Simulation results that confirm the theory are given.]]>648195319652138<![CDATA[A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC]]>2.]]>648196619762550<![CDATA[A 29.5 dBm Class-E Outphasing RF Power Amplifier With Efficiency and Output Power Enhancement Circuits in 45nm CMOS]]>648197719883479<![CDATA[Class-J<sub>2</sub> Power Amplifiers]]>2 Mode Power Amplifier,” which provides higher efficiency and output power compared with conventional class-J mode counterpart. This mode of operation is realized by injection of the second-harmonic current to drain node of a class-J power amplifier (PA) to reduce the 45° phase shift between drain current and voltage signals. Similar to class-J PAs, the second-harmonic impedance of class-J_{2} PAs is purely reactive to simplify the design of the output matching network. The auxiliary second-harmonic injection circuit comprises a transistor biased in class-B mode followed by a class-C biased amplifier to achieve high second-harmonic current conversion efficiency. Theoretical formulations suggest that a 5% improvement in drain efficiency ($\eta _{D}$ ) as well as a 1.5-dB increase in output power can be achieved for the class-J_{2} mode in comparison with the typical class-J operation. To check the accuracy of theoretical predictions, a proof-of-concept 1-GHz class-J_{2} PA with 12.2-dBm output power and 43% PAE is implemented in a 0.18-$\mu \text{m}$ CMOS technology. For better comparison, a 1-GHz class-J PA with the same transistor size and bias condition as the class-J_{2} PA is also fabricated. The output power and PAE of the reference class-J PA are 11.4 dBm and 40.6%, respectively, which are in agreement with theoretical predictions.]]>648198920027176<![CDATA[Optically Powered Optical Transmitter Using a Single Light-Emitting Diode]]>$\mu \text{m}$ process can be powered directly without losing efficiency to a sustained voltage boosting scheme. Higher voltage is needed only during brief transmissions. A scalable, inverter-based, switched capacitor voltage boosting transmitter drives the LED in short pulses with 93% electrical energy efficiency. Three consecutive pulses are sent as preamble symbol, two as logic 0 and one as logic 1. The microsystem features a $\Delta V_{{\text {BE}}}$ -based temperature sensor with a data-dependent partial conversion scheme to save energy. The sensor expends 1 nJ/full conversion at 5 kSa/s and 0.25 nJ/partial conversion at 20 kSa/s. The transmitter can serially output data at 1 nJ/pulse; 10-cm detection distance is achieved under 6-mW/mm^{2} light intensity using an in-house photodiode detector circuit. The circuitry dissipates 6 $\mu \text{W}$ in total at 1.2-V nominal voltage. It consists of a 0.1-mm^{2} LED die, 2.25-mm^{2} IC, and a surface mounted device storage capacitor, taking approximately 1-mm^{3} volume.]]>648200320122101<![CDATA[Systematic Computation of Nonlinear Bilateral Dynamical Systems With a Novel Low-Power Log-Domain Circuit]]>$\mu \text{m}$ technology. The resulting continuous-time, continuous-value, and low-power circuits exhibit various bifurcation phenomena, nominal time-domain responses in good agreement with their mathematical counterparts and fairly acceptable process variation results (less than 5% STD).]]>6482013202512648<![CDATA[An 80-mV-to-1.8-V Conversion-Range Low-Energy Level Shifter for Extremely Low-Voltage VLSIs]]>$\mu \text{m}$ CMOS technology was able to convert an extremely low-voltage input of 80 mV into a high-voltage output of 1.8 V. The energy of the proposed LS was 0.35 pJ, when the low supply voltage, high supply voltage, and input pulse frequency were 0.4 V, 1.8 V, and 10 kHz, respectively. The static power dissipation without input was 0.12 nW.]]>648202620353206<![CDATA[Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling]]>MIN) of 0.45 V among the half-select free SRAM cells. The test chip with 65-nm CMOS technology shows that the proposed 9T SRAM is fully operated at 0.35 V and 25 °C condition. Under the supply voltages between 0.35 and 1.1 V, the 4-kb SRAM macro is operated between 640 kHz and 560 MHz, respectively. The proposed 9T SRAM shows the best voltage scalability without any assist circuit while maintaining small macro area and fast operation frequency.]]>648203620483466<![CDATA[Theoretical Model of E<sup>n</sup>DP to Achieve Energy-Efficient SRAM]]>n-delay product (E^{n}DP, n>1) for energy efficiency design is proposed in this paper. Compared with the conventional energy-delay product metric, the new metric puts more weight on energy than delay, more suitable for those power-critical mid/low-speed applications. We first establish the theoretical model, and then provide comprehensive optimum design points for various processes and applications as energy-efficient design guidelines. We also find that the optimum E^{n}DP operation coincides with the well-known near-threshold methodology, and discuss the challenges and possible design methods. An enhanced hierarchical bit-line structure along with 8T-SRAM cell and local read/write assist circuits is introduced for robust operation and energy efficiency improvement, facilitating E^{n}DP methodology. Finally, an 8-kb SRAM macro in 180-nm CMOS technology for ultra-low-power applications is designed and fabricated to validate the methodology, where a supply voltage of 1.54 $\text{V}_{\mathrm {TH}}$ is applied to obtain maximum energy efficiency based on E^{2}DP metric. The minimum E^{2}DP of 610 pJ^{2}/GHz is obtained at 0.65 V, fitting the theoretical analysis accurately. Power consumption at 0.65 V is $14.89~\mu \text{W}$ , only 2.6% of that at nominal voltage, 1.8 V. The test chip can operate correctly from 1.8to 0.6 V with frequency scaling from 400 to 15.5 MHz.]]>648204920624109<![CDATA[SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis]]>648206320722640<![CDATA[A Novel Framework to Estimate the Path Delay Variability On the Back of an Envelope via the Fan-Out-of-4 Metric]]>648207320854383<![CDATA[Toward Practical Code-Based Signature: Implementing Fast and Compact QC-LDGM Signature Scheme on Embedded Hardware]]>648208620972045<![CDATA[Robust Set-Membership Normalized Subband Adaptive Filtering Algorithms and Their Application to Acoustic Echo Cancellation]]>$L_{0}$ norm constraint robust set-membership NSAF ($L_{0}$ -RSM-NSAF), robust set-membership improved proportionate NSAF (RSM-IPNSAF), and $L_{0}$ norm constraint robust set-membership improved proportionate NSAF ($L_{0}$ -RSM-IPNSAF) algorithms are derived by minimizing a differentiable cost function that utilizes the Riemannian distance between the updated and previous weight vectors as well as the $L_{0}$ norm of the weighted updated weight vector. Simulations in AEC application confirm the improvements of the proposed algorithms in performance.]]>648209821112115<![CDATA[Fully-Digital Blind Compensation of Non-Linear Distortions in Wideband Receivers]]>648211221234941<![CDATA[Memristor Crossbar for Adaptive Synchronization]]>$N^{2}$ , where $N$ is the number of nonlinear circuits to be synchronized). This issue is solved in this paper by adopting a memristor crossbar architecture for adaptive synchronization. The functionality of the structure is demonstrated, with respect to different switching characteristics, via a simulation-based evaluation using a behavioral threshold-type model of voltage-controlled bipolar memristor. In addition, we show that the architecture is robust to device variability and faults: quite surprisingly, when faults are localized, the performance of the approach may also improve as adaptation becomes more significant.]]>648212421331675<![CDATA[Efficient Verification Against Undesired Operating Points for MOS Analog Circuits]]>648213421452199<![CDATA[A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies]]>geometrical representation with unary operators of multivalued logic. The geometric representation facilitates scanning appropriately to obtain simple sum-of-products expressions in terms of unary operators. An implementation based on Python is described. The power of the approach lies in its applicability to a wide variety of circuits. The proposed approach leads to the savings of 26% and 22% in transistor-count, respectively, for a ternary full-adder and a ternary content-addressable memory (TCAM) over the best existing designs. Furthermore, the proposed approach requires, on an average, less than 10% of the number of the transistors in comparison with a recent decoder-based design for various ternary benchmark circuits. Extensive HSPICE simulation results show roughly 92% reduction in power-delay product (PDP) for a $12\times 12$ TCAM and 60% reduction in PDP for a 24-ternary digit barrel shifter over recent designs.]]>648214621593833<![CDATA[Optimal VLSI Delay Tuning by Space Tapering With Clock-Tree Application]]>® processor designs, operated in 800-MHz and 1.6-GHz clock speed, respectively, and confirmed its viability for delivering the required useful skews to flip-flops. About 90% of the useful skew problems could be solved by shielding manipulations.]]>648216021701823<![CDATA[Iterative Learning Control for Multi-Agent Systems With Finite-Leveled Sigma-Delta Quantization and Random Packet Losses]]>$\Sigma \Delta$ ) quantization and random packet losses is first proposed in this paper. To realize the digital communication between signals and utilize limited communication bandwidth effectively, we introduce the $\Sigma \Delta$ quantizer with limited communication data rate (quantization bits) into the control field and for the design of the QILC in this paper. In addition, the packet losses are also first considered into the QILC, which makes the controller more close to the practical engineering applications. Since the nonlinearity and randomness introduced by the quantization and packet losses, a decreasing learning gain is utilized with the help of the non-smooth analysis and mathematical expectation for the analysis of convergence. Accurate tracking in the sense of expectation can be obtained based on randomly small number of quantization bits, even merely one bit of quantization information. Numerical simulations are given to show the effectiveness of the proposed protocol.]]>648217121811753<![CDATA[Multi-Carrier Chaos Shift Keying: System Design and Performance Analysis]]>648218221942122<![CDATA[Effect of Offset Mismatch in Time-Interleaved ADC Circuits on OFDM-BER Performance]]>648219522062348<![CDATA[Topology Derivation and Analysis of Integrated Multiple Output Isolated DC–DC Converters With Stacked Configuration for Low-Cost Applications]]>$N$ -output isolated converter, which employs $2N$ primary switches, only $N$ +1 switches are required in the primary side of proposed converters to independently regulate $N$ secondary output voltages. Therefore, the number of switches is greatly reduced, contributing to lower cost. In this paper, detailed topology derivation is first introduced. A diversity of integrated multiple output topologies is derived with different cell connections and different cell configurations, including the asymmetrical flyback, forward as well as a half-bridge. Their performance characteristics are different and thus they are suitable for different applications. Then, in order to obtain a comprehensive insight of the proposed converters, a simplified dual-output asymmetrical flyback converter with three primary switches is taken as an example to be introduced in detail. Each output voltage in the converter is regulated with individual duty cycle, and zero-voltage-switching operation is achieved for all switches over the whole load range. Finally, experimental results based on a prototype circuit with two 12-V/3-A and 5-V/4.8-A outputs are also provided to validate converter effectiveness.]]>648220722183809<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors]]>6482219221986<![CDATA[IEEE Open Access Publishing]]>648222022201369<![CDATA[IEEE Circuits and Systems Society Information]]>648C3C3113