http://ieeexplore.ieee.org TOC Alert for Publication# 8919 2013 May 23 60 6 C1 C4 153 60 6 C2 C2 134 $I_{D}$ and less than 10% for $R_{rm out}$ and $G_{m}$. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 22 and 90 nm nodes with less than a 5% error. Several other 90 and 22 nm analog blocks are successfully emulated by the 45 nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H).]]> 60 6 1369 1380 2121 60 6 1381 1394 3405 60 6 1395 1406 2464 $mu$ V. In the asynchronous level crossing ADC, the minimum delta resolution is 4 mV. The input signal frequency of the ADC is up to 5 kHz. The system was fabricated using the AMI 0.5 $mu$ m CMOS process. The chip size is 1.5 mm by 1.5 mm. The power consumption of the 4-channel system from a 3.3 V supply is 118.8 $mu$W in the static state and 501.6 $mu$W with a 240 kS/s sampling rate. The conversion efficiency is 1.6 nJ/conversion.]]> 60 6 1407 1418 2151 $mu{rm m}$ CMOS devices from the BCD6s process of STMicroelectroncs. The prototype occupies a total area of 1025$,times,$ 515 ${rm mm}^{2}$ and is marked by a power consuption of 84 $mu{rm W}$. The input capacitance range is 0–256 fF, with a resolution of 0.8 fF and a temperature sensitivity of 300 ${rm ppm}/^{circ}{rm C}$.]]> 60 6 1419 1431 2494 $,times,$VDD output buffers is proposed, where the threshold voltages (Vth) of PMOSs and NMOSs varying with process and temperature deviation could be detected, respectively. A prototype 2$,times,$ VDD output buffer using the proposed compensation design is fabricated using a typical 0.18 $mu$ m CMOS process. By adjusting output currents, the slew rate of output signals could be compensated over 117%. The maximum data rate with compensation is 120 MHz in contrast with 95 MHz without compensation, which is measured on silicon with an equivalent probe capacitive load of 10 pF.]]> 60 6 1432 1440 1910 ${rm mm}^{2}$ and a power consumption of 101.5 mW in the worst case.]]> 60 6 1441 1454 2502 60 6 1455 1468 3726 60 6 1469 1477 1955 60 6 1478 1486 1185 ${2^{n},2^{n}-1,2^{n}+1,2^{n}-2^{(n+1)/2}+1,2^{n}+2^{(n+1)/2}+1}$ , with an equivalent $5n$ -bit dynamic range, and propose horizontal and vertical extensions in order to improve the parallelism and increase the dynamic range. The vertical extensions increase the value of the power-of-2 modulus in the five-moduli set. With the horizontal extensions, new six channel sets are allowed by introducing the $2^{n+1}+1$ or $2^{n-1}+1$ moduli. This paper proposes methods to design memoryless reverse converters for the proposed moduli sets with large dynamic ranges, up to $(8n+1)$-bit. Due to the complexity of the reverse conversion, both the Chinese Remainder Theorem and the Mixed Radix Conversion are applied in the proposed methods to derive efficient reverse converters. Experimental results suggest that the proposed vertical extensions allow to reduce the area-delay-product up to 1.34 times in comparison with the related state-of-the-art. The horizontal extensions allow larger and more balanced moduli sets, resulting in an improvement of the RNS arithmetic computation, at the cost of lower reverse conversion performance.]]> 60 6 1487 1500 4284 60 6 1501 1510 1610 60 6 1511 1520 1753 $Omega$ and 10 M$Omega$ . A verilog-A model derived from a full 3-D simulation of the PCM cell was developed to simulate the complete chip. The chip was used to demonstrate operation at 2 bit/cell and programming below 10 $mu$s with Ge $_{2}$Sb $_{2}$Te $_{5}$ (GST) based PCM cells at a raw bit error rate of ${sim} 2 times 10^{- 4}$. Two main roadblocks for MLC PCM are drift and endurance. The accuracy of the analog frontend in combination with the programmable controller enables drift mitigation at the system level and the exploration of new materials for MLC operation at $3{+}$ bit/cell.]]> 60 6 1521 1533 2632 60 6 1534 1547 2345 $L_1-L_2$ minimization problem. Simulation results in system-identification and channel-equalization applications are presented which demonstrate that improved steady-state misalignment, tracking capability, and readaptation can be achieved relative to those in some state-of-the-art competing algorithms.]]> 60 6 1548 1558 2381 60 6 1559 1569 2496 We classify these fully nonlinear circuit elements in terms of the variables involved in their constitutive relations and the notions of the differential- and the state-order of a device. We extend the notion of a topologically degenerate configuration to this broader context, and characterize the differential-algebraic index of nodal models of such circuits. Additionally, we explore certain dynamical features of mem-circuits involving manifolds of non-isolated equilibria. Related bifurcation phenomena are explored for a family of nonlinear oscillators based on mem-devices.]]> 60 6 1570 1583 1979 60 6 1584 1594 2694 60 6 1595 1607 4036 60 6 1608 1620 3020 ${{Sigma}} {{Delta}}$ Modulation. First the intrinsic bandwidth limits of multi-level switching amplifiers are inferred, to clearly state the advantages and limitations of multi-level power amplification. From the existing analyses of Pulse Width Modulation already reported in the literature, PWM is herein extended to multiple levels based on an equivalent representation, which allows to derive a closed expression for the power spectrum of multi-level PWM in bandlimited signal tracking. The Asynchronous ${{Sigma}} {{Delta}}$ Modulation is extended to multiple levels and the resulting multi-level encoding algorithm is analyzed in both time and frequency domains. The performance of both modulations is characterized and compared at different operating frequencies and using different number of levels. The main outcomes of this in-depth characterization show that, if the switching frequency is high enough, the tracking error is independent of the modulation and the switching frequency, i.e., it only depends upon the number of levels, which points out the suitability of asynchronous modulations for relatively low switching frequencies (compared to the number of levels).]]> 60 6 1621 1634 3224 $n$ -bands using $1mapsto n$ frequency transformations. The effect of the transformations on the bandwidth of the matching network and the effect of inductor losses on the transducer loss of the matching network are analyzed. A strategy to improve the efficiency of the matching networks in the presence of lossy components has been proposed. Applications of the proposed synthesis technique in the development and design of new multi-band LNA/PA architectures are discussed in detail with the help of design examples. In one of the design examples, the circuit has been prototyped and measured results are presented.]]> 60 6 1635 1647 1751 $mu{rm m}$ CMOS mixed-signal 2P4M 3.3/5 V polycide process with a die area of $1.56times 1.47 {rm mm}^{2}$. The output voltage is fixed at 3.3 V, while the input voltage range is 1.8–5 V. The maximal load current for a 1.8-V input voltage is 10 mA, while it increases to 30 mA when the input voltage is larger than 3 V.]]> 60 6 1648 1656 2071 60 6 1657 1669 2258 60 6 1670 1677 1783 60 6 1679 1679 1156 60 6 1680 1680 1372 60 6 C3 C3 117