<![CDATA[ IEEE Transactions on Circuits and Systems I: Regular Papers - new TOC ]]>
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TOC Alert for Publication# 8919 2017January 19<![CDATA[Table of contents]]>641C1C4169<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers publication information]]>641C2C272<![CDATA[Update From the Editor-in-Chief]]>64112648<![CDATA[Frequency-Channelized Mismatch-Shaped Quadrature Data Converters for Carrier Aggregation in MU-MIMO LTE-A]]>6413132915<![CDATA[The Effects of Inter-Symbol Interference in Dynamic Element Matching DACs]]>64114231350<![CDATA[A Class of 1-Bit Multi-Step Look-Ahead $Sigma $ - $Delta $ Modulators]]> - modulators are introduced. They improve upon the stability and noise shaping characteristics of conventional 1-bit - modulators by minimizing quantization error metrics of the current and future output samples. The mathematical model of the proposed MSLA modulators is analyzed. It is shown that the MSLA modulators are equivalent to a system of conventional - modulators in parallel, but with a common multi-input 1-bit quantizer instead of a typical one. The properties of this multi-input quantizer are studied and the transfer functions of the MSLA modulators are derived. Simulation results are presented demonstrating the advantages of the MSLA modulators over conventional 1-bit - ones in a number of applications. A parametric hardware architecture of the MSLA modulators is presented offering an adjustable trade-off between performance and hardware complexity based on the number of look-ahead steps. Finally, a FPGA implementation of a MSLA modulator is presented along with simulation results.]]>64124372464<![CDATA[A CMOS Pixel With Embedded ADC, Digital CDS and Gain Correction Capability for Massively Parallel Imaging Array]]> CMOS technology. The size of the pixel with 9-bit resolution is . Measurements of the pixel array confirm functionality of the proposed solution. CDS reduces dark FPN from 12 LSB (3%) to 0.8 LSB (0.2%) and light FPN from 14 LSB (3.7%) to 7 LSB (1.8%). Further reduction of the light FPN (to ~1 LSB) was achieved by compensating PRNU using massively parallel innovative digital multiplication which features good resolution (1/511), does not disturb CDS executed at the same time, and can be implemented within a small pixel area.]]>64138493345<![CDATA[A Two-Step Prediction ADC Architecture for Integrated Low Power Image Sensors]]> 256-pixel prototype chip was fabricated using a 0.35 CMOS technology with a pixel footprint of . The fill factor is 49%. 10-bit successive approximation register (SAR) ADCs are used in the column-parallel ADC array.]]>64150602841<![CDATA[A Numerical Methodology for the Analysis of Switched-Capacitor Filters Taking Into Account Non-Ideal Effects of Switches and Amplifiers]]>64161711224<![CDATA[New Results and Techniques for Computation of Stored Energy in Lossless/All-Pass Systems]]>6417285935<![CDATA[Post-Quantum Cryptography on FPGA Based on Isogenies on Elliptic Curves]]> , and minimizing pipeline stalls with optimal scheduling. Consequently, our results are also faster than software libraries running affine SIDH even on Intel Haswell processors. For our implementation at 85-bit quantum security and 128-bit classical security, we generate ephemeral public keys in 1.655 million cycles for Alice and 1.490 million cycles for Bob. We generate the shared secret in an additional 1.510 million cycles for Alice and 1.312 million cycles for Bob. On a Virtex-7, these results are approximately 1.5 times faster than known software implementations running the same 512-bit SIDH. Our results and observations show that the isogeny-based schemes can be implemented with high efficiency on reconfigurable hardware.]]>64186992769<![CDATA[A Hybrid Time Borrowing Technique to Improve the Performance of Digital Circuits in the Presence of Variations]]>6411001102279<![CDATA[A Reverse Converter and Sign Detectors for an Extended RNS Five-Moduli Set]]> where is a positive odd integer and is nonnegative integer such that . The paper proposes an efficient residue-to-binary converter along with a converter-based sign detector for this extended set. The paper also presents a residue-to-residue transformer that transforms the same five-moduli set to the three-moduli set . Such a transformer enables the five-moduli set to utilize components that are (or will be) designed for the three-moduli set such as sign detectors.]]>6411111211178<![CDATA[Dynamic Dual-Reference Sensing Scheme for Deep Submicrometer STT-MRAM]]> increase in average SM, and a ~ 70% reduction in average BER, compared with conventional sensing schemes.]]>6411221322004<![CDATA[A Bias-Bounded Digital True Random Number Generator Architecture]]>6411331442201<![CDATA[Analysis of Encoding Degradation in Spiking Sensors Due to Spike Delay Variation]]> and queueing delay are evaluated on two encoding mechanisms which have been used for implementations of silicon array spiking sensors: asynchronous delta modulation and self-timed reset. As specific examples, is obtained from a 2T current-mode comparator, and is obtained from an M/D/1 queue for 1-D sensors like the silicon cochlea and an /D/1 queue for 2-D sensors like the silicon retina. Quantitative relations between the SDR and the circuit and system parameters of spiking sensors are established. The analysis method presented in this work will be useful for future specifications-guided designs of spiking sensors.]]>6411451553324<![CDATA[Statistical Analysis for Pattern-Dependent Simultaneous Switching Outputs (SSO) of Parallel Single-Ended Buffers]]>6411561693250<![CDATA[Reliable Output Feedback Control of Discrete-Time Fuzzy Affine Systems With Actuator Faults]]> static output feedback (SOF) control for nonlinear systems with actuator faults in a descriptor system framework. The nonlinear plant is characterized by a discrete-time Takagi-Sugeno (T-S) fuzzy affine model with parameter uncertainties, and the Markov chain is utilized to describe the actuator-fault behaviors. Specifically, by adopting a state-output augmentation approach, the original system is firstly reformulated into the descriptor fuzzy affine system. Based upon a novel piecewise Markovian Lyapunov function (LF), the performance analysis condition for the underlying system is then presented, and furthermore the robust and reliable SOF controller synthesis is carried out. It is shown that by invoking the redundancy properties induced by the descriptor formulation, combined with some convexifying techniques, the existence of the desired reliable controller can be explicitly determined by the solution of a convex optimization problem. Finally, simulation studies are applied to confirm the effectiveness of the developed method.]]>6411701811113<![CDATA[A 4.7-Gb/s Reconfigurable CMOS Imaging Optical Receiver Utilizing Adaptive Spectrum Balancing Equalizer]]> matrix of Spatially Modulated Light detectors (SML), each with 730-MHz bandwidth followed by on-chip switches are integrated to allow the detection of photodiodes (PDs) in Line of Sight (LOS) with the transmitter. The imaging optical receiver employs a novel adaptive equalizer that uses spectrum reshaping to equalize the low bandwidth of the SML PD and partially compensate for the variable capacitance seen by the transimpedance amplifier resulting from dynamic LOS variations. Implemented in 130-nm CMOS technology, the chip provides an optical sensitivity of -3.5 dBm for nm modulated light with 4.7-Gb/s random data at , and -4.4 dBm at 4.5 Gb/s with , using one activated PD. For the case when all nine PDs are activated, corresponding to 11.5 pF total PDs capacitance at the input of the transimpedance amplifier, measurement results show a sensitivity of -5 dBm for 2-Gb/s data at . The total power consumption including the differential output buffer is 97 mW from a single 1.5-V supply while providing 750-mV peak to peak output voltage over the differential resistance of the measurement equipment. The total die area including bond pads is .]]>6411821944421<![CDATA[Self-Learning RF Receiver Systems: Process Aware Real-Time Adaptation to Channel Conditions for Low Power Operation]]>6411952073152<![CDATA[Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA]]>6412082162407<![CDATA[A 220-mV Power-on-Reset Based Self-Starter With 2-nW Quiescent Power for Thermoelectric Energy Harvesting Systems]]>6412172263502<![CDATA[Series-Parallel Charge Pump Conditioning Circuits for Electrostatic Kinetic Energy Harvesting]]>6412272401317<![CDATA[IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors]]>64124124167<![CDATA[IEEE Access]]>641242242633<![CDATA[Introducing IEEE Collabratec]]>6412432432161<![CDATA[IEEE Open Access Publishing]]>6412442441357<![CDATA[IEEE Circuits and Systems Society Information]]>641C3C369