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		<title><![CDATA[ Nanotechnology, IEEE Transactions on - new TOC ]]></title>
		<link>http://ieeexplore.ieee.org</link>
		<description>TOC Alert for Publication# 7729 </description>
		<year>2013</year>
		<month>May      </month>
		<day>21</day>
		<item>
			<title><![CDATA[Front Cover]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514118]]></link>
			<description><![CDATA[Presents the cover/table of contents for this issue of the periodical.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514118]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>C1</startPage>
			<endPage>C1</endPage>
			<fileSize>200</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Transactions on Nanotechnology publication information]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514155]]></link>
			<description><![CDATA[Provides a listing of current staff, committee members and society officers.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514155]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>C2</startPage>
			<endPage>C2</endPage>
			<fileSize>137</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[Table of contents]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514101]]></link>
			<description><![CDATA[Presents the table of contents for this issue of the periodical.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514101]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>277</startPage>
			<endPage>278</endPage>
			<fileSize>138</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[Interface State Density of Single Vertical Nanowire MOS Capacitors]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6468107]]></link>
			<description><![CDATA[An investigation of trap states at the semiconductor&#x2013;oxide interface of single silicon nanowires is presented using vertical gate-all-around nanowire MOS capacitors. By performing highly accurate capacitance&#x2013;voltage measurements at room temperature, the energetic distribution of interface traps <formula formulatype="inline"><tex Notation="TeX">$D_{{rm it}}$</tex></formula> could be extracted with the quasi-static method. Although the capacitance of a single nanowire MOS capacitor with Al<formula formulatype="inline"><tex Notation="TeX">$_2$</tex> </formula>O<formula formulatype="inline"><tex Notation="TeX">$_3$</tex></formula> gate oxide is only 2 fF, <formula formulatype="inline"><tex Notation="TeX">$D_{{rm it}}$</tex></formula> values were obtained with good reproducibility. For etched, vertical Si nanowires, <formula formulatype="inline"><tex Notation="TeX">$D_{{rm it}}$</tex></formula> in the range of <formula formulatype="inline"><tex Notation="TeX">$(4 pm 1) times 10^{12},rm {cm^{-2}eV^{-1}}$</tex></formula> was obtained.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6468107]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>279</startPage>
			<endPage>282</endPage>
			<fileSize>441</fileSize>
			<authors><![CDATA[Mensch, P.;Moselund, K.E.;Karg, S.;Lortscher, E.;Bjork, M.T.;Riel, H.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Efficient Multiternary Digit Adder Design in CNTFET Technology]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6475189]]></link>
			<description><![CDATA[This letter presents an efficient multiternary digit (trit) adder design in carbon nanotube field effect transistor technology. The adder is based on an efficient single-trit full-adder design with low-complexity encoder and reduced complexity carry-generation unit. Further, we optimize the number of encoder and decoder blocks required while putting together several single-trit full-adder units to realize a multitrit adder. Extensive HSPICE simulation results show roughly 79&#x0025; reduction in power-delay product for three-trit adders and 88 <formula formulatype="inline"><tex Notation="TeX">$hbox{%}$</tex></formula> reduction in power-delay product for nine-trit adders in comparison to a direct realization.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6475189]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>283</startPage>
			<endPage>287</endPage>
			<fileSize>920</fileSize>
			<authors><![CDATA[Sridharan, K.;Gurindagunta, S.;Pudi, V.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Immunity to Device Variations in a Spiking Neural Network With Memristive Nanodevices]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6508962]]></link>
			<description><![CDATA[Memristive nanodevices can feature a compact multilevel nonvolatile memory function, but are prone to device variability. We propose a novel neural network-based computing paradigm, which exploits their specific physics, and which has virtual immunity to their variability. Memristive devices are used as synapses in a spiking neural network performing unsupervised learning. They learn using a simplified and customized &#x201C;spike timing dependent plasticity&#x201D; rule. In the network, neurons&#x2019; threshold is adjusted following a homeostasis-type rule. We perform system level simulations with an experimentally verified model of the memristive devices&#x2019; behavior. They show, on the textbook case of character recognition, that performance can compare with traditional supervised networks of similar complexity. They also show that the system can retain functionality with extreme variations of various memristive devices&#x2019; parameters (a relative standard dispersion of more than 50&#x0025; is tolerated on all device parameters), thanks to the robustness of the scheme, its unsupervised nature, and the capability of homeostasis. Additionally the network can adjust to stimuli presented with different coding schemes, is particularly robust to read disturb effects and does not require unrealistic control on the devices&#x2019; conductance. These results open the way for a novel design approach for ultraadaptive electronic systems.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6508962]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>288</startPage>
			<endPage>295</endPage>
			<fileSize>493</fileSize>
			<authors><![CDATA[Querlioz, D.;Bichler, O.;Dollfus, P.;Gamrat, C.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Characterization and Analysis of the Hysteresis in a ZnO Nanoparticle Thin-Film Transistor]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6401196]]></link>
			<description><![CDATA[During the past few decades, the interest in flexible and transparent electronics has arisen, and ZnO-based devices present a great potential among these technologies. In this study, ZnO nanoparticles were used to integrate thin-film transistors, whereas cross-linked poly(4-vinylphenol) (PVP) and PECVD-SiO <formula formulatype="inline"><tex Notation="TeX">$_{2}$</tex></formula> were used as a gate dielectric layer. Unfortunately, there are reliability concerns in ZnO devices, such as aging and hysteresis. In this study, an experimental investigation of the hysteresis in the transfer characteristic is performed. It was observed that the hysteresis direction is affected by temperature variation when the polymeric dielectric is used. The PVP bulk polarization, the traps in nanoparticles and at the polymeric dielectric interface, as well as the desorption of oxygen molecules in the surface of the nanoparticles, were attributed as the main cause of the hysteretic behavior.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6401196]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>296</startPage>
			<endPage>303</endPage>
			<fileSize>1310</fileSize>
			<authors><![CDATA[Vidor, F.F.;Wirth, G.;Assion, F.;Wolff, K.;Hilleringmann, U.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Nanoindentation-Induced Pop-In Effects in GaN Thin Films]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6412803]]></link>
			<description><![CDATA[The nanoindentation-induced pop-in phenomena in GaN thin film are investigated using Berkovich indenters. The formation of dislocation rosettes revealed by cathodoluminescence (CL) spectroscopy is found to closely relate with the pop-in effect displayed in depth-sensitive measurements. Namely, the CL images of the indented spots show well-defined rosette structures consistent with the hexagonal symmetry of GaN, indicating that the distribution of deformation-induced extended defects/dislocations may dramatically affect the CL emission. The use of CL thus may provide an alternative means for studying the near-surface plasticity in other semiconductor thin films, as well.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6412803]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>304</startPage>
			<endPage>308</endPage>
			<fileSize>339</fileSize>
			<authors><![CDATA[Jian, S.-R.;Juang, J.-Y.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Nanowire Thermocouple Characterization Platform]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6461418]]></link>
			<description><![CDATA[Thermocouples fabricated out of nanowires possess a high spatial and temporal resolution. Due to their small size, nanowires exhibit different physical properties from their bulk counterparts. One of these properties, the Seebeck coefficient, specifies how well the thermocouple converts a temperature gradient into an open-circuit voltage. We have developed a characterization platform, with which the Seebeck coefficient of nanowires can be measured as required for the calibration of nanowire thermocouples and optimization of their fabrication process.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6461418]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>309</startPage>
			<endPage>313</endPage>
			<fileSize>490</fileSize>
			<authors><![CDATA[Szakmany, G.P.;Krenz, P.M.;Schneider, L.C.;Orlov, A.O.;Bernstein, G.H.;Porod, W.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Physical Parameters to Enhance AC Magnetically Induced Heating Power of Ferrite Nanoparticles for Hyperthermia in Nanomedicine]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6461960]]></link>
			<description><![CDATA[Solid-state ferrimagnetic MFe<formula formulatype="inline"><tex Notation="TeX">$_{2}$</tex></formula>O <formula formulatype="inline"><tex Notation="TeX">$_{4}$</tex></formula> (M &#x003D; Mg, Ni, Co; mean diameter size <formula formulatype="inline"><tex Notation="TeX">$d$</tex></formula> &#x003D; 30&#x2013;35&#x00A0;nm) and superparamagnetic MFe <formula formulatype="inline"><tex Notation="TeX">$_{2}$</tex></formula>O<formula formulatype="inline"><tex Notation="TeX">$_{4}$</tex></formula> (M &#x003D; Mg, Ni, Mn<formula formulatype="inline"><tex Notation="TeX">$_{0.5}$</tex></formula>Zn<formula formulatype="inline"><tex Notation="TeX"> $_{0.5}$</tex></formula>; <formula formulatype="inline"><tex Notation="TeX">$d$</tex></formula> &#x003D; 6&#x2013;8&#x00A0;nm) nanoparticles &#x005B;ferromagnetic nanoparticles (FMNPs) and superparamagnetic nanoparticles (SPNPs)&#x005D; were used to explore the physical mechanisms of ac magnetically induced heating and identify what physical parameters would be the most critical to enhance the ac magnetically induced heating power for local in vivo hyperthermia agent applications. It was experimentally confirmed that &#x201C;dc (minor) hysteresis loss power&#x201D; generated by the magnetization reversal process, and &#x201C;N&#x00E9;el relaxation loss power&#x201D; generated by fluctuation of the magnetic moment dominantly contribute to the ac heat generation of FMNPs and SPNPs, respectively. In addition, all the experimentally and physically analyzed results demonstrated that the improvement of in-phase magnetic susceptibility <formula formulatype="inline"><tex Notation="TeX">$chi^prime _m$</tex></formula> is directly relevant to the &#x201C;dc (minor) hysteresis loss power&#x201D; as well as the dc magnetic softness, and the out-of-phase magnetic susceptibility <formula formulatype="inline"><tex Notation="TeX">$chi^{prime prime} _m$</tex></formula> is directly relevant to the &#x201C;N&#x00E9;el relaxation l-
ss power (or ac magnetic hysteresis loss power, A )&#x201D; as well as the ac magnetic softness are the most crucial physical parameters responsible for enhancing the ac magnetically induced heating power of solid-state FMNPs and SPNPs, respectively. Particularly, some technical and engineering approaches, which can improve the <formula formulatype="inline"><tex Notation="TeX">$chi^prime _m$</tex> </formula> of FMNPs and the <formula formulatype="inline"><tex Notation="TeX">$chi^{prime prime} _m$</tex></formula> of SPNPs, were proposed and introduced in this study to provide crucial information how to effectively design and develop a new promising hyperthermia agent in nanomedicine.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6461960]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>314</startPage>
			<endPage>322</endPage>
			<fileSize>1177</fileSize>
			<authors><![CDATA[Jeun, M.;Lee, S.;Kim, Y.J.;Jo, H.Y.;Park, K.H.;Paek, S.H.;Takemura, Y.;Bae, S.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Single-Walled Carbon Nanotube Pirani Gauges Prepared by DEP Assembly]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6464598]]></link>
			<description><![CDATA[This paper reports the design, fabrication, and characteristics of the single-walled carbon nanotubes (SWNTs) Pirani gauge fabricated by dielectrophoretic assembly first which requires simple equipments and process, costs little, and operates at room temperature without limitation on the materials of electrode and substrate. Its theory and design were described in detail. The characteristics were measured and analyzed systematically such as current&#x2013;voltage, resistance&#x2013;temperature, thermal response, resistance&#x2013;pressure, and power consumption properties. The results show that this SWNTs Pirani gauge has rapid thermal response of milliseconds and can operate at very low power consumption down to 15 nW. It reveals a wide linear dynamic range from 0.8 to 80 000 Pa and high sensitivity about 8 k&#x03A9;/Pa on average.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6464598]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>323</startPage>
			<endPage>329</endPage>
			<fileSize>652</fileSize>
			<authors><![CDATA[Yu, F.;Zhang, J.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Computing With Nonequilibrium Ratchets]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6466388]]></link>
			<description><![CDATA[Electronic ratchets transduce local spatial asymmetries into directed currents in the absence of a global drain bias by rectifying temporal signals that reside far from the thermal equilibrium. We show that the absence of a drain bias can provide distinct energy advantages for computation, specifically, reducing static dissipation in a logic circuit. Since the ratchet functions as a gate voltage-controlled current source, it also potentially reduces the dynamic dissipation associated with charging/discharging capacitors. In addition, the unique charging mechanism eliminates timing-related constraints on logic inputs, in principle allowing for adiabatic charging. We calculate the ratchet currents in classical and quantum limits, and show how a sequence of ratchets can be cascaded to realize universal Boolean logic.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6466388]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>330</startPage>
			<endPage>339</endPage>
			<fileSize>721</fileSize>
			<authors><![CDATA[Kabir, M.;Unluer, D.;Li, L.;Ghosh, A.W.;Stan, M.R.;]]></authors>
		</item>
		<item>
			<title><![CDATA[RF Linearity Potential of Carbon-Nanotube Transistors Versus MOSFETs]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6466389]]></link>
			<description><![CDATA[Carbon-nanotube, field-effect transistors (CNFETs) are among the candidates for emerging radio-frequency applications, and improved linearity has recently been identified as one of the performance advantages they might offer. In this paper, the potential for improved linearity has been investigated by considering an array-based device structure under the best-case scenario of ballistic transport. A nonlinear equivalent circuit for ballistic field-effect transistors is used to compare the linearity of CNFETs to conventional MOSFETs. We show that nanotube devices working at high frequencies are not inherently linear, as recently suggested in the literature, and that CNFETs exhibit overall linearity that is comparable to their MOSFET counterparts. The nonlinear quantum capacitance is identified to be a major source of high-frequency nonlinearity in CNFETs. The impacts of device parameters such as oxide capacitance, channel width, and tube pitch are also investigated.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6466389]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>340</startPage>
			<endPage>351</endPage>
			<fileSize>1783</fileSize>
			<authors><![CDATA[Alam, A.U.;Rogers, C.M.S.;Paydavosi, N.;Holland, K.D.;Ahmed, S.;Vaidyanathan, M.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Localized Synthesis of Carbon Nanotube Films on Suspended Microstructures by Laser-Assisted Chemical Vapor Deposition]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6468108]]></link>
			<description><![CDATA[A laser-assisted chemical vapor deposition (LCVD) method has been developed for in situ synthesis of carbon nanotube (CNT) films on suspended microstructures. Focused laser beams are used to heat locally the suspended microstructures with low thermal mass and low thermal dissipation to high temperatures for localized CNT growth. Other substrate areas than the microstructures remain at low temperatures, preventing the devices on the substrate from being destroyed by high temperatures. The synthesizing parameters and the influences on CNT morphology and structures are systematically investigated and optimized, and solutions for uniform temperature distribution are proposed. Upon optimization, uniform, localized, and rapid growth of CNT synthesis has been achieved on suspended microstructures, and aligned CNTs with length and uniformity comparable to conventional hot-wall CVD have been successfully obtained. The experimental results show LCVD is a promising technology for in situ and localized synthesis of CNT films on suspended microstructures for CNT-CMOS (complementary metal oxide semiconductor) integration.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6468108]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>352</startPage>
			<endPage>360</endPage>
			<fileSize>1093</fileSize>
			<authors><![CDATA[Li, Y.;Ruan, W.;Wang, Z.;]]></authors>
		</item>
		<item>
			<title><![CDATA[A Plasmonic MIM Frequency Diplexer]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6470687]]></link>
			<description><![CDATA[A plasmonic frequency diplexer in a metal&#x2013;insulator&#x2013;metal waveguide at mid-infrared range is presented. The diplexer consists of two bandpass filters connected to a power splitter. A circuit-based model is used to successfully design the configuration. The effect of metal loss is carefully considered in our simulations. The performance of the designed diplexer is outstanding in terms of the frequency selectivity and loss. The proposed scheme is scalable in the infrared range and can also be used to realize frequency multiplexers.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6470687]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>361</startPage>
			<endPage>367</endPage>
			<fileSize>689</fileSize>
			<authors><![CDATA[Farmahini-Farahani, M.;Mosallaei, H.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Quantum Dot Cellular Automata Check Node Implementation for LDPC Decoders]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6473892]]></link>
			<description><![CDATA[The quantum dot Cellular Automata (QCA) is an emerging nanotechnology that has gained significant research interest in recent years. Extremely small feature sizes, ultralow power consumption, and high clock frequency make QCA a potentially attractive solution for implementing computing architectures at the nanoscale. To be considered as a suitable CMOS substitute, the QCA technology must be able to implement complex real-time applications with affordable complexity. Low density parity check (LDPC) decoding is one of such applications. The core of LDPC decoding lies in the check node (CN) processing element which executes actual decoding algorithm and contributes toward overall performance and complexity of the LDPC decoder. This study presents a novel QCA architecture for partial parallel, layered LDPC check node. The CN executes Normalized Min Sum decoding algorithm and is flexible to support CN degree <formula formulatype="inline"><tex Notation="TeX">$dc$</tex></formula> up to 20. The CN is constructed using a VHDL behavioral model of QCA elementary circuits which provides a hierarchical bottom up approach to evaluate the logical behavior, area, and power dissipation of the whole design. Performance evaluations are reported for the two main implementations of QCA i.e. molecular and magnetic.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6473892]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>368</startPage>
			<endPage>377</endPage>
			<fileSize>1096</fileSize>
			<authors><![CDATA[Awais, M.;Vacca, M.;Graziano, M.;Roch, M.R.;Masera, G.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Precise Analytical Model for Short-Channel Quadruple-Gate Gate-All-Around MOSFET]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6476737]]></link>
			<description><![CDATA[A compact analytical model is presented for crossover point, subthreshold slope, virtual cathode position, and threshold voltage for a short-channel quadruple-gate (QuaG) gate-all-around (GAA) MOSFET. The potential distribution in the channel is obtained by an analytical solution of 3-D Poisson&#x2019;s equation, where the electron quasi-Fermi level is approximated to be zero for low drain-to-source voltages. Using isomorphic polynomial function for potential distribution, we have analyzed, for the first time, the crossover point for the QuaG GAA MOSFET. Further, the modeled subthreshold slope for lightly doped QuaG GAA MOSFET has been improved by introducing <formula formulatype="inline"><tex Notation="TeX">$hbox{it z}$</tex></formula>-dependent characteristic length, and the position of minimum center potential in the channel is obtained by virtual cathode position. A model is proposed for threshold voltage, based on shifting of the inversion charge from center line to silicon&#x2013;insulator interface.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6476737]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>378</startPage>
			<endPage>385</endPage>
			<fileSize>1365</fileSize>
			<authors><![CDATA[Sharma, D.;Vishvakarma, S.K.;]]></authors>
		</item>
		<item>
			<title><![CDATA[NEM Relay-Based Sequential Logic Circuits for Low-Power Design]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6480881]]></link>
			<description><![CDATA[Nanoelectromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behaves like an ideal switch. The zero leakage operation has generated lot of interest in low power logic design using these relays <citerefgrp><citeref refid="ref1"/></citerefgrp>, <citerefgrp><citeref refid="ref2"> </citeref></citerefgrp>. This paper presents various sequential circuit topologies using NEM relays and analyzes their power, performance, and area tradeoffs. The mechanical delay is inversely proportional to the gate-base voltage <formula formulatype="inline"><tex Notation="TeX">$V_{gb}$</tex></formula>. This paper also presents an integrated voltage doubler-based flip-flop that improves the performance by 2<formula formulatype="inline"><tex Notation="TeX">$times$</tex></formula> by overdriving <formula formulatype="inline"><tex Notation="TeX">$V_{gb}$</tex></formula>. An electromechanical model which accounts for the mechanical, electrical, and dispersion effects of the suspended gate relay operating at 1&#x00A0;V with a nominal air gap of 5&#x2013;10 nm has been developed based on published fabrication results in <citerefgrp> <citeref refid="ref1"/></citerefgrp>. Three sequential logic benchmark circuits were designed using NEM relays to verify the correctness of operation of the proposed circuits. This study explores different relay-based latch and flip-flop topologies, proposes fast sequential circuits that can operate at a frequency of <formula formulatype="inline"><tex Notation="TeX">$1/2t_{m}$</tex></formula> (theoretical fastest frequency for NEM relay logic circuits) and further improves speed of sequential circuits by distributed charge boosting.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6480881]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>386</startPage>
			<endPage>398</endPage>
			<fileSize>2553</fileSize>
			<authors><![CDATA[Venkatasubramanian, R.;Manohar, S.K.;Balsara, P.T.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Systolic Pattern Matching Hardware With Out-of-Plane Nanomagnet Logic Devices]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6481449]]></link>
			<description><![CDATA[We present the design and simulation of systolic information processing hardware that is comprised of single domain, Co/Pt magnets (i.e., out-of-plane nanomagnet logic or oNML). The designed circuit can identify instances of a preprogrammed bit sequence in streaming data. The systolic architecture 1) exploits unique benefits of the oNML device architecture such as nonvolatility and inherently pipelined logic with no memory overhead for holding the bits in the pipeline and 2) mitigates less desirable features of oNML such as nearest neighbor dataflow and longer device switching times when compared to a CMOS transistor. The designed layout is verified and analyzed by micromagnetic simulations. We quantify how the performance and energy of oNML information processing hardware compares to CMOS equivalents and conclude that the initial oNML design (including the overhead of magnetic field generation) is about an order of magnitude more power efficient at essentially iso-performance.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6481449]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>399</startPage>
			<endPage>407</endPage>
			<fileSize>851</fileSize>
			<authors><![CDATA[Ju, X.;Niemier, M.T.;Becherer, M.;Porod, W.;Lugli, P.;Csaba, G.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Paper-Based Lithium-Ion Batteries Using Carbon Nanotube-Coated Wood Microfibers]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6481448]]></link>
			<description><![CDATA[Lithium-ion batteries using flexible paper-based current collectors have been developed. These current collectors were fabricated from wood microfibers that were coated with carbon nanotubes (CNT) through an electrostatic layer-by-layer nanoassembly process. The carbon nanotube mass loading of the presented (CNT-microfiber paper) current collectors is 10.1&#x00A0;&#x03BC;g/cm<formula formulatype="inline"><tex Notation="TeX">$^{2}$</tex></formula>. The capacities of the batteries made with the current collectors are 150&#x00A0;mAh/g for lithium cobalt oxide (LCO) half-cell, 158&#x00A0;mAh/g for lithium titanium oxide (LTO) half-cell, and 126&#x00A0;mAh/g for LTO/LCO full-cell. The fabrication approach of the CNT-microfiber paper current collectors, the assembly of the batteries, and the experimental results are presented and discussed.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6481448]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>408</startPage>
			<endPage>412</endPage>
			<fileSize>650</fileSize>
			<authors><![CDATA[Aliahmad, N.;Agarwal, M.;Shrestha, S.;Varahramyan, K.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Sneak-Path Testing of Crossbar-Based Nonvolatile Random Access Memories]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6482250]]></link>
			<description><![CDATA[Emerging nonvolatile memory (NVM) technologies, such as resistive random access memories (RRAM) and phase-change memories (PCM), are an attractive option for future memory architectures due to their nonvolatility, high density, and low-power operation. Notwithstanding these advantages, they are prone to high defect densities due to the nondeterministic nature of the nanoscale fabrication. We examine the fault models and propose an efficient testing technique to test crossbar-based NVMs. The typical approach to testing memories entails testing one memory element at a time. This is time consuming and does not scale for the dense, RRAM or PCM-based memories. We propose a testing scheme based on &#x201C;sneak-path sensing&#x201D; to efficiently detect faults in the memory. The testing scheme uses sneak paths inherent in crossbar memories, to test multiple memory elements at the same time, thereby reducing testing time. We designed the design-for-test support necessary to control the number of sneak paths that are concurrently enabled; this helps control the power consumed during test. The proposed scheme enables and leverages sneak paths during test mode, while still maintaining a sneak path free crossbar during normal operation.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6482250]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>413</startPage>
			<endPage>426</endPage>
			<fileSize>928</fileSize>
			<authors><![CDATA[Kannan, S.;Rajendran, J.;Karri, R.;Sinanoglu, O.;]]></authors>
		</item>
		<item>
			<title><![CDATA[A Dual-Gate Graphene FET Model for Circuit Simulation&#x2014;SPICE Implementation]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6482646]]></link>
			<description><![CDATA[This paper presents a SPICE compatible model of a dual-gate bilayer graphene field-effect transistor. The model describes the functionality of the transistor in all the regions of operation for both hole and electron conduction. We present closed-form analytical equations that define the boundary points between the regions to ensure Jacobian continuity for efficient circuit simulator implementation. A saturation displacement current is proposed to model the drain current when the channel becomes ambipolar. The model proposes a quantum capacitance that varies with the surface potential. The model has been implemented in Berkeley SPICE-3, and it shows a good agreement against experimental data with the normalized root-mean-square error less than <formula formulatype="inline"><tex Notation="TeX">$10%$</tex> </formula>.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6482646]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>427</startPage>
			<endPage>435</endPage>
			<fileSize>609</fileSize>
			<authors><![CDATA[Umoh, I.J.;Kazmierski, T.J.;Al-Hashimi, B.M.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Electrical Characteristics for Flash Memory With Germanium Nitride as the Charge-Trapping Layer]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6484984]]></link>
			<description><![CDATA[Due to a larger band offset and a higher permittivity compared to Si<formula formulatype="inline"><tex Notation="TeX"> $_{3}$</tex></formula>N<formula formulatype="inline"><tex Notation="TeX">$_{4}$</tex></formula>, Ge<formula formulatype="inline"><tex Notation="TeX"> $_{3}$</tex></formula>N<formula formulatype="inline"><tex Notation="TeX">$_4$</tex></formula> formed by NH <formula formulatype="inline"><tex Notation="TeX">$_{3}$</tex></formula> plasma nitridation of an amorphous Ge film was explored in this study as the charge-trapping layer for flash memory devices. As the nitridation time prolongs, memory window and operation speed are improved accordingly. The improvement is inferred to be the increased number of trapping sites and higher permittivity of the charge-trapping layer caused by the introduction of nitrogen atoms. The former is helpful in storing more charges while the latter offers a higher electric field over the tunnel oxide. Memory devices with 180-s NH<formula formulatype="inline"><tex Notation="TeX">$_{3}$</tex></formula> plasma nitridation hold great potential for advanced memory applications because they possess many promising characteristics such as a large hysteresis memory window, high operation speed, robust endurance performance up to 10<formula formulatype="inline"><tex Notation="TeX">$^{5}$</tex></formula> program/erase (P/E) cycles, and good retention characteristic with 15&#x0025; charge loss after 10-year operation at 85&#x00A0;&#x00B0;C.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6484984]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>436</startPage>
			<endPage>441</endPage>
			<fileSize>648</fileSize>
			<authors><![CDATA[Lin, C.-C.;Wu, Y.-H.;Lin, Y.-S.;Wu, M.-L.;Chen, L.-L.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Modeling of Plasmon Resonances of Multiple Flat Noble-Metal Nanostrips With a Median-Line Integral Equation Technique]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6493447]]></link>
			<description><![CDATA[The surface plasmon and the periodicity-induced resonances in the scattering and absorption of light by multiple flat nanosize noble-metal strips are investigated using a new efficient model. It exploits the fact that the nanostrip thickness is a small fraction of the wavelength in the visible range. This justifies shrinking the strip cross section to its median line and using the generalized boundary conditions on that line, with the strip thickness entering the coefficients. As a result, the scattering problem is reduced to the singular and hypersingular integral equations. We discretize them using quadrature formulas of interpolation type and build an algorithm having guaranteed convergence and controlled accuracy of computations. It enables fast simulation of structures consisting of many noble-metal strips. Near- and far-field characteristics for finite flat grating of silver and gold nanostrips are presented.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6493447]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>442</startPage>
			<endPage>449</endPage>
			<fileSize>2906</fileSize>
			<authors><![CDATA[Shapoval, O.V.;Sauleau, R.;Nosich, A.I.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Spike-Timing-Dependent Plasticity Using Biologically Realistic Action Potentials and Low-Temperature Materials]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6493449]]></link>
			<description><![CDATA[Spike-timing-dependent plasticity (STDP) is a fundamental learning rule observed in biological synapses that is desirable to replicate in neuromorphic electronic systems. Nanocrystalline-silicon thin film transistors (TFTs) and memristors can be fabricated at low temperatures, and are suitable for use in such systems because of their potential for high density, 3-D integration. In this paper, a compact and robust learning circuit that implements STDP using biologically realistic nonmodulated rectangular voltage pulses is demonstrated. This is accomplished through the use of a novel nanoparticle memory-TFT with short retention time at the output of the neuron circuit that drives memristive synapses. Similarities to biological measurements are examined with single and repeating spike pairs or different timing intervals and frequencies, as well as with spike triplets.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6493449]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>450</startPage>
			<endPage>459</endPage>
			<fileSize>820</fileSize>
			<authors><![CDATA[Subramaniam, A.;Cantley, K.D.;Bersuker, G.;Gilmer, D.;Vogel, E.M.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Designing LPG-OADM Based on a Finite Element Method and an Eigenmode Expansion Method]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6494308]]></link>
			<description><![CDATA[This study proposes a visual, graphical, and simplistic numerical simulation method for a long period fiber gratings optical add-drop multiplexer (LPG-OADM), as opposed to the well-known traditional mode-coupled theory. This method combines the finite element method and the eigenmode expansion method, where the finite element method is used to solve all existing guided modes. The eigenmode expansion method was used to calculate the energy transfer phenomenon of the guided modes in the LPG-OADM. This study provides a detailed explanation of the key reasons why the periodic structure of the LPG-OADM can achieve significantly superior results for our method compared to those obtained using other numerical methods, such as the finite-difference time-domain and beam propagation methods. All existing numerical simulation methods focus on large-sized periodic components; only the method established in this study has 3-D design and analysis capabilities. This study used actual examples to verify that, under the operating wavelength of &#x03BB; &#x003D; 1550&#x00A0;nm, the LPG-OADM designed using this method would have the full-width half-maximum of 0.2846&#x00A0;nm, and an insertion loss and homo-dyne crosstalk of nearly 0. That is, the LPG-OADM designed using this method can reach the ITU specification for the dense wavelength-division multiplexer bandwidth. The primary objective of this study is to use the combination of these two numerical simulation methods in conjunction with a rigorous, simple, and comprehensive design flow to provide a graphical and simplistic simulation technique that reduces the learning time and professional threshold requirements for the design and application of LPG-OADM.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6494308]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>460</startPage>
			<endPage>471</endPage>
			<fileSize>1418</fileSize>
			<authors><![CDATA[He, Y.J.;Chen, X.Y.;]]></authors>
		</item>
		<item>
			<title><![CDATA[2013 International Electronic Device Meeeting]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514144]]></link>
			<description><![CDATA[Describes the above-named upcoming conference event. May include topics to be covered or calls for papers.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514144]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>472</startPage>
			<endPage>472</endPage>
			<fileSize>304</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Transactions on Nanotechnology information for authors]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514095]]></link>
			<description><![CDATA[Provides instructions and guidelines to prospective authors who wish to submit manuscripts.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514095]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>C3</startPage>
			<endPage>C3</endPage>
			<fileSize>101</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[[Blank page - back cover]]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514111]]></link>
			<description><![CDATA[This page or pages intentionally left blank.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514111]]></guid>
			<volume>12</volume>
			<issue>3</issue>
			<startPage>C4</startPage>
			<endPage>C4</endPage>
			<fileSize>5</fileSize>
			<authors><![CDATA[]]></authors>
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