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		<title><![CDATA[ Circuits and Systems for Video Technology, IEEE Transactions on - new TOC ]]></title>
		<link>http://null</link>
		<description>TOC Alert for Publication# 76 </description>
		<year>2013</year>
		<month>May      </month>
		<day>20</day>
		<item>
			<title><![CDATA[Table of contents]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6512089]]></link>
			<description><![CDATA[Presents the cover/table of contents for this issue of the periodical.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6512089]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>C1</startPage>
			<endPage>C1</endPage>
			<fileSize>64</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Transactions on Circuits and Systems for Video Technology publication information]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6512067]]></link>
			<description><![CDATA[Provides a listing of current staff, committee members and society officers.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6512067]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>C2</startPage>
			<endPage>C2</endPage>
			<fileSize>140</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[Quaternion-Based Impulse Noise Removal From Color Video Sequences]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6232451]]></link>
			<description><![CDATA[In this paper, a new quaternion vector filter for removal of random impulse noise in color video sequences is presented. First, luminance distances and chromaticity differences that are represented in quaternion form are combined together to measure color distances between color pixels. Then, based on this new color distance mechanism, the samples along horizontal, vertical, and diagonal directions in current frame and the samples of adjacent frames on motion trajectory are used to detect whether each pixel is noisy or not. By analyzing the spatiotemporal order-statistic information about these directional samples, the video pixels are classified into noise free and noisy. Finally, 3-D weighted vector median filtering is performed on the pixels that are judged as noisy, and the other pixels remain unchanged. The experimental results show that the proposed algorithm significantly outperforms other state-of-the-art video denoising methods in terms of both objective measure and visual evaluation.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6232451]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>741</startPage>
			<endPage>755</endPage>
			<fileSize>2111</fileSize>
			<authors><![CDATA[Jin, L.;Liu, H.;Xu, X.;Song, E.;]]></authors>
		</item>
		<item>
			<title><![CDATA[The Nature-Inspired BASIS Feature Descriptor for UAV Imagery and Its Hardware Implementation]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6327642]]></link>
			<description><![CDATA[This paper presents a feature descriptor well suited for limited-resource applications such as an unmanned aerial vehicle embedded systems, small microprocessors, and small low-power field programmable gate array (FPGA) fabric. The basis sparse-coding inspired similarity (BASIS) descriptor utilizes sparse coding to create dictionary images that model the regions in the human visual cortex. Due to the reduced amount of computation required for computing BASIS descriptors, reduced descriptor size, and the ability to create the descriptors without the use of a floating point, this approach is an excellent candidate for FPGA hardware implementation. The bit-level-accurate BASIS descriptor was tested on a dataset of real aerial images with the task of calculating a frame-to-frame homography and compared to software versions of scale-invariant feature transform (SIFT) and speeded-up robust features (SURF). Experimental results show that the BASIS descriptor outperforms SIFT and performs comparably to SURF on frame-to-frame aerial feature point matching. BASIS descriptors require less memory storage than other descriptors and can be computed entirely in hardware, allowing the descriptor to operate at real-time frame rates on a low-power embedded platform such as an FPGA.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6327642]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>756</startPage>
			<endPage>768</endPage>
			<fileSize>1504</fileSize>
			<authors><![CDATA[Fowers, S.G.;Lee, D.-J.;Ventura, D.A.;Archibald, J.K.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Low Complexity Mode Decision and Motion Estimation for H.264/AVC Based Depth Maps Encoding in Free Viewpoint Video]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6327640]]></link>
			<description><![CDATA[Within free viewpoint video, the 3-D reconstruction of the scene is created from a high number of viewpoints. Every viewpoint is represented by a traditional sequence, called texture, and its associated depth information. This is known as a View plus Depth environment. In this paper, a novel low complexity mode decision and motion estimation algorithm for the H.264/AVC based encoding of depth sequences is proposed. Given that a texture sequence and its associated depth represent the same scene from the same point of view, they should have similar motion characteristics. The complexity reduction of the depth encoding, in the proposed algorithm, is obtained by taking advantage of the texture motion information that has been previously processed by a traditional H.264/AVC encoder. The characteristics of depth and texture sequences are analyzed, focusing on similarities and differences that are properly managed to design an algorithm able to detect when the motion information of the texture might be usefully exploited in the encoding of the corresponding depth sequence. The proposed method is able to achieve the same objective quality, measured by means of the PSNR and the VQM, than a traditional H.264/AVC encoder with a reduction of up to 58% of the computational burden.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6327640]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>769</startPage>
			<endPage>783</endPage>
			<fileSize>1965</fileSize>
			<authors><![CDATA[Cernigliaro, G.;Jaureguizar, F.;Cabrera, J.;Garcia, N.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Efficient Disparity Estimation Using Hierarchical Bilateral Disparity Structure Based Graph Cut Algorithm With a Foreground Boundary Refinement Mechanism]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6329939]]></link>
			<description><![CDATA[The disparity estimation problem is commonly solved using graph cut (GC) methods, in which the disparity assignment problem is transformed to one of minimizing global energy function. Although such an approach yields an accurate disparity map, the computational cost is relatively high. Accordingly, this paper proposes a hierarchical bilateral disparity structure (HBDS) algorithm in which the efficiency of the GC method is improved without any loss in the disparity estimation performance by dividing all the disparity levels within the stereo image hierarchically into a series of bilateral disparity structures of increasing fineness. To address the well-known foreground fattening effect, a disparity refinement process is proposed comprising a fattening foreground region detection procedure followed by a disparity recovery process. The efficiency and accuracy of the HBDS-based GC algorithm are compared with those of the conventional GC method using benchmark stereo images selected from the Middlebury dataset. In addition, the general applicability of the proposed approach is demonstrated using several real-world stereo images.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6329939]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>784</startPage>
			<endPage>801</endPage>
			<fileSize>2016</fileSize>
			<authors><![CDATA[Wang, Y.-C.;Tung, C.-P.;Chung, P.-C.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Adaptive Computationally Scalable Motion Estimation for the Hardware H.264/AVC Encoder]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6328253]]></link>
			<description><![CDATA[Motion estimation is the most computationally intensive part of video encoders, as the compression efficiency usually increases with the amount of computations. The adaptive computationally scalable motion-estimation algorithm and its hardware implementation described in this paper allow the H.264/AVC encoders to achieve efficiencies close to optimal in real-time conditions. The algorithm employs several search strategies to adapt to local motion activity, and the number of checked search points is set by the encoder controller for each macroblock. The algorithm can achieve results close to optimum even if the number of search points assigned to macroblocks is strongly limited and varies over time. The architecture applies a novel dataflow. First, the motion vector generation is not constrained by the calculation of residuals and corresponding costs. Second, the fractional-pel interpolation is performed prior to the integer-pel search. Third, the ME and compensation use the same resources. The architecture is verified in the real-time field-programmable gate array hardware encoder. The synthesis results and the real-time verification show that the design can support HDTV at 200 MHz for 0.13-<formula formulatype="inline"><tex Notation="TeX">$mu{rm m}$</tex></formula> TSMC technology.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6328253]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>802</startPage>
			<endPage>812</endPage>
			<fileSize>1180</fileSize>
			<authors><![CDATA[Pastuszak, G.;Jakubowski, M.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Architecture of a Low Latency Image Rectification Engine for Stereoscopic 3-D HDTV Processing]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6328256]]></link>
			<description><![CDATA[The emerging market of digital 3-D film productions in HD resolution leads to the need for high-quality equipment in the production chain. The incoming video streams of the two cameras require an image rectification due to unavoidable misalignments within the stereoscopic camera setup. This rectification can either take place in postprocessing of the recorded material or it can be applied in real time during the shooting. Especially in the case of streaming and recording of live events, real-time processing is necessary and, additionally, the system has to provide a very low latency. We present a hardware image rectification engine, which supports the processing of stereo high-definition serial digital interfaces video streams with up to 1080p30 video with a latency below 1 ms. The image rectification engines for the two channels are implemented on two Altera Stratix III EP3SL340 running at 74.25 MHz. They can be controlled by the stereoscopy analysis software, which calculates the parameters required for the image rectification at runtime.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6328256]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>813</startPage>
			<endPage>822</endPage>
			<fileSize>927</fileSize>
			<authors><![CDATA[Hubert, H.;Stabernack, B.;Zilly, F.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Reconfigurable Processor for Binary Image Processing]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6329416]]></link>
			<description><![CDATA[Binary image processing is a powerful tool in many image and video applications. A reconfigurable processor is presented for binary image processing in this paper. The processor's architecture is a combination of a reconfigurable binary processing module, input and output image control units, and peripheral circuits. The reconfigurable binary processing module, which consists of mixed-grained reconfigurable binary compute units and output control logic, performs binary image processing operations, especially mathematical morphology operations, and implements related algorithms more than 200 f/s for a 1024<formula formulatype="inline"> <tex Notation="TeX">$,times,$</tex></formula>1024 image. The periphery circuits control the whole image processing and dynamic reconfiguration process. The processor is implemented on an EP2S180 field-programmable gate array. Synthesis results show that the presented processor can deliver 60.72 GOPS and 23.72 <formula formulatype="inline"><tex Notation="TeX">${rm GOPS/mm}^{2}$</tex></formula> at a 220-MHz system clock in the SMIC 0.18-<formula formulatype="inline"><tex Notation="TeX">$mu{rm m}$</tex></formula> CMOS process. The simulation and experimental results demonstrate that the processor is suitable for real-time binary image processing applications.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6329416]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>823</startPage>
			<endPage>831</endPage>
			<fileSize>809</fileSize>
			<authors><![CDATA[Zhang, B.;Mei, K.;Zheng, N.;]]></authors>
		</item>
		<item>
			<title><![CDATA[A 182 mW 94.3 f/s in Full HD Pattern-Matching Based Image Recognition Accelerator for an Embedded Vision System in 0.13-<formula formulatype="inline"> <img src="/images/tex/16813.gif" alt="\mu{\rm m}"> </formula> CMOS Technology]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6328252]]></link>
			<description><![CDATA[A pattern-matching based image recognition accelerator (PRA) is presented for embedded vision applications. It is a hardware accelerator that performs interest point detection and matching for image-based recognition applications in real time in both mobile devices and vehicles. The proposed system is implemented as a small IP, and it has eight times higher throughput than state-of-the-art object recognition processors, which are implemented based on a heterogeneous many-core system. PRA has three key features: 1) joint algorithm&#x2013;architecture optimizations for exploiting bit-level parallelism; 2) a low-power unified hardware platform for interest point detection and matching; and 3) scalable hardware architecture. PRA achieves <formula formulatype="inline"> <tex Notation="TeX">$9.5times$</tex></formula> performance improvement with only 30% of logic gates including static random-access memory (SRAM) compared to the state-of-the-art object recognition processors. It consists of 78.3 k logic gates and 128 kB SRAM, which are integrated in a test chip implemented for PRA verification. It achieves 94.3 frames per second (fps) in 1080 p full HD resolution at 200-MHz operating frequency while consuming 182 mW. Each complete operation for interest point detection and matching requires 2.09 cycles and 8 cycles on average, respectively, based on a unified bit-level matching accelerator, which is implemented only with 680 logic gates.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6328252]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>832</startPage>
			<endPage>845</endPage>
			<fileSize>1487</fileSize>
			<authors><![CDATA[Park, J.-S.;Kim, H.-E.;Kim, L.-S.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Fast Mode Decision Algorithm for the H.264/AVC Scalable Video Coding Extension]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6340317]]></link>
			<description><![CDATA[A fast mode decision algorithm for efficient implementation of the scalable video coding (SVC) extension of H.264/AVC is described. SVC incorporates interlayer prediction, a new tool that exploits as much lower layer information as possible in order to improve the coding efficiency of the enhancement layer. However, it also greatly increases the computational complexity. A fast mode selection algorithm that exploits the correlation of a macroblock in the enhancement layer and both the colocated macroblocks in the base layer and neighboring macroblocks in the enhancement layer is proposed. The algorithm examines the level of picture details and motion activity, and utilizes the mode information of the base layer to make faster enhancement layer decisions and thus save coding time. Simulation results show that the proposed algorithm reduces encoding by up to 84% compared with the JSVM 9.18 implementation. This is achieved without any noticeable degradation in rate distortion.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6340317]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>846</startPage>
			<endPage>855</endPage>
			<fileSize>477</fileSize>
			<authors><![CDATA[Lu, X.;Martin, G.R.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Detecting Group Activities With Multi-Camera Context]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6341064]]></link>
			<description><![CDATA[Human group activities detection in multi-camera CCTV surveillance videos is a pressing demand on smart surveillance. Previous works on this topic are mainly based on camera topology inference that is hard to apply to real-world unconstrained surveillance videos. In this paper, we propose a new approach for multi-camera group activities detection. Our approach simultaneously exploits intra-camera and inter-camera contexts without topology inference. Specifically, a discriminative graphical model with hidden variables is developed. The intra-camera and inter-camera contexts are characterized by the structure of hidden variables. By automatically optimizing the structure, the contexts are effectively explored. Furthermore, we propose a new spatiotemporal feature, named vigilant area (VA), to characterize the quantity and appearance of the motion in an area. This feature is effective for group activity representation and is easy to extract from a dynamic and crowded scene. We evaluate the proposed VA feature and discriminative graphical model extensively on two real-world multi-camera surveillance video data sets, including a public corpus consisting of 2.5 h of videos and a 468-h video collection, which, to the best of our knowledge, is the largest video collection ever used in human activity detection. The experimental results demonstrate the effectiveness of our approach.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6341064]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>856</startPage>
			<endPage>869</endPage>
			<fileSize>1093</fileSize>
			<authors><![CDATA[Zha, Z.-J.;Zhang, H.;Wang, M.;Luan, H.;Chua, T.-S.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Visual Object Tracking Based on Local Steering Kernels and Color Histograms]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6340318]]></link>
			<description><![CDATA[In this paper, we propose a visual object tracking framework, which employs an appearance-based representation of the target object, based on local steering kernel descriptors and color histogram information. This framework takes as input the region of the target object in the previous video frame and a stored instance of the target object, and tries to localize the object in the current frame by finding the frame region that best resembles the input. As the object view changes over time, the object model is updated, hence incorporating these changes. Color histogram similarity between the detected object and the surrounding background is employed for background subtraction. Experiments are conducted to test the performance of the proposed framework under various conditions. The proposed tracking scheme is proven to be successful in tracking objects under scale and rotation variations and partial occlusion, as well as in tracking rather slowly deformable articulated objects.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6340318]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>870</startPage>
			<endPage>882</endPage>
			<fileSize>1165</fileSize>
			<authors><![CDATA[Zoidi, O.;Tefas, A.;Pitas, I.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Generalized Gradient Vector Flow for Snakes: New Observations, Analysis, and Improvement]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6419796]]></link>
			<description><![CDATA[Snakes, or active contours, have been widely used in image processing applications. An external force for snakes called gradient vector flow (GVF) attempts to address traditional snake problems of initialization sensitivity and poor convergence to concavities, while generalized GVF (GGVF) aims to improve GVF snake convergence to long and thin indentations (LTIs). In this paper, we find and show that both GVF and GGVF snakes essentially yield the same performance in capturing LTIs of odd widths, and generally neither can converge to even-width LTIs. Based on a thorough investigation of the GVF and GGVF fields within the LTI during their iterative processes, we identify the crux of the convergence problem, and accordingly propose a novel external force termed as component-normalized GGVF (CN-GGVF) to eliminate the problem. CN-GGVF is obtained by normalizing each component of initial GGVF vectors with respect to its own magnitude. Experimental results and comparisons against GGVF snakes show that the proposed CN-GGVF snakes can capture LTIs regardless of odd or even widths with a remarkably faster convergence speed, while preserving other desirable properties of GGVF snakes with lower computational complexity in vector normalization.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6419796]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>883</startPage>
			<endPage>897</endPage>
			<fileSize>2137</fileSize>
			<authors><![CDATA[Qin, L.;Zhu, C.;Zhao, Y.;Bai, H.;Tian, H.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Sample and Pixel Weighting Strategies for Robust Incremental Visual Tracking]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6471191]]></link>
			<description><![CDATA[In this paper, we introduce the incremental temporally weighted principal component analysis (ITWPCA) algorithm, based on singular value decomposition update, and the incremental temporally weighted visual tracking with spatial penalty (ITWVTSP) algorithm for robust visual tracking. ITWVTSP uses ITWPCA for computing incrementally a robust low dimensional subspace representation (model) of the tracked object. The robustness is based on the capacity of weighting the contribution of each single sample to the subspace generation to reduce the impact of bad quality samples, reducing the risk of model drift. Furthermore, ITWVTSP can exploit the a priori knowledge about important regions of a tracked object. This is done by penalizing the tracking error on some predefined regions of the tracked object, which increases the accuracy of tracking. Several tests are performed on several challenging video sequences, showing the robustness and accuracy of the proposed algorithm, as well as its superiority with respect to state-of-the-art techniques.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6471191]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>898</startPage>
			<endPage>911</endPage>
			<fileSize>1189</fileSize>
			<authors><![CDATA[Cruz-Mota, J.;Bierlaire, M.;Thiran, J.-P.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Deinterlacing Using Taylor Series Expansion and Polynomial Regression]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6414619]]></link>
			<description><![CDATA[This paper introduces an efficient intra-field deinterlacing algorithm that is based on Taylor series expansion and polynomial regression. In order to estimate the value of an interpolated point using the given data, we rely on a generic local approximation function around this point for estimating the missing data. The well known <formula formulatype="inline"><tex Notation="TeX">$N$</tex></formula>-term Taylor series expansion is regarded as a local representation of the approximation function, and we use polynomial regression to find the optimal local approximation of the function. Instead of estimating the edge orientations as in previous intra-field deinterlacing methods, such as an edge-based line average, we propose an efficient deinterlacing method, which does not consider directional difference measurements that use limited candidate directions. When compared with existing deinterlacing algorithms, the proposed algorithm improves the peak signal-to-noise-ratio while maintaining a high efficiency.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6414619]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>912</startPage>
			<endPage>917</endPage>
			<fileSize>438</fileSize>
			<authors><![CDATA[Wang, J.;Jeon, G.;Jeong, J.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Open Access]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6512091]]></link>
			<description><![CDATA[Advertisement: This publication offers open access options for authors. IEEE open access publishing.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6512091]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>918</startPage>
			<endPage>918</endPage>
			<fileSize>1156</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Xplore Digital Library]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6512079]]></link>
			<description><![CDATA[??Advertisement: IEEE Xplore digital library. Driving research at the world's leading universities and institutions.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6512079]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>919</startPage>
			<endPage>919</endPage>
			<fileSize>1372</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Global History Network]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6512082]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6512082]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>920</startPage>
			<endPage>920</endPage>
			<fileSize>3171</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Circuits and Systems Society Information]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6512066]]></link>
			<description><![CDATA[Provides a listing of current committee members and society officers.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6512066]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>C3</startPage>
			<endPage>C3</endPage>
			<fileSize>117</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Transactions on Circuits and Systems for Video Technology information for authors]]></title>
			<link><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6512088]]></link>
			<description><![CDATA[Provides instructions and guidelines to prospective authors who wish to submit manuscripts.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://null/xpl/articleDetails.jsp?arnumber=6512088]]></guid>
			<volume>23</volume>
			<issue>5</issue>
			<startPage>C4</startPage>
			<endPage>C4</endPage>
			<fileSize>107</fileSize>
			<authors><![CDATA[]]></authors>
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