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		<title><![CDATA[ Device and Materials Reliability, IEEE Transactions on - new TOC ]]></title>
		<link>http://ieeexplore.ieee.org</link>
		<description>TOC Alert for Publication# 7298 </description>
		<year>2012</year>
		<month>February </month>
		<day>10</day>
		<item>
			<title><![CDATA[Front cover]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094100]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094100]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>C1</startPage>
			<endPage>C1</endPage>
			<fileSize>97</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Transactions on Device and Materials Reliability publication information]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094103]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094103]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>C2</startPage>
			<endPage>C2</endPage>
			<fileSize>36</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[Table of Contents]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094099]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094099]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>505</startPage>
			<endPage>505</endPage>
			<fileSize>42</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[What is in a Page Charge?]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094107]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094107]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>506</startPage>
			<endPage>506</endPage>
			<fileSize>17</fileSize>
			<authors><![CDATA[Jindal, R. P.;Street, R.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Editorial Kudos to Our Reviewers]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094108]]></link>
			<description><![CDATA[Lists the reviewers who contributed to IEEE Transactions on Device and Materials Reliability in 2011.]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094108]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>507</startPage>
			<endPage>507</endPage>
			<fileSize>16</fileSize>
			<authors><![CDATA[Oates, T.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Introduction to the Special Section on Electrostatic Discharge: From Transistor Technology to Chip Level to System Level]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094106]]></link>
			<description><![CDATA[The three papers in this special section were originally presented at the 2010 EOS/ESD Symposium at Reno, Nevada.]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094106]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>508</startPage>
			<endPage>508</endPage>
			<fileSize>17</fileSize>
			<authors><![CDATA[Duvvury, C.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Triggering of Transient Latch-up by System-Level ESD]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6021340]]></link>
			<description><![CDATA[This paper investigates the influences of temperature and the trigger parameters (width and rise time) on the threshold of transient latch-up (TLU). It is shown that temperature is a much more critical parameter than transient trigger parameters. For high discharge currents which are typical for system-level surges as, e.g., seen in cable discharge events, even very short trigger pulses can cause TLU.]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6021340]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>509</startPage>
			<endPage>515</endPage>
			<fileSize>688</fileSize>
			<authors><![CDATA[Brodbeck, T.;Stadler, W.;Baumann, C.;Esmark, K.;Domanski, K.;]]></authors>
		</item>
		<item>
			<title><![CDATA[ESD Engineering Fully Silicided Large MOSFET Driver for Maximum <formula formulatype="inline"> <img src="/images/tex/20036.gif" alt="It\hbox {1}"> </formula> Performance]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6036163]]></link>
			<description><![CDATA[Simultaneous optimization of LDD and antipunch-through implant conditions for ESD performance of very large width silicided output driver NMOSFET without snapback mode of operation is reported. Physical mechanisms responsible for performance improvement and device sensitivity to pulse rise time, with little or no dependence on TLP pulsewidth, are detailed.]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6036163]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>516</startPage>
			<endPage>521</endPage>
			<fileSize>594</fileSize>
			<authors><![CDATA[Iyer, N.M.;Jiang Hao;Yap Hin Kiong;Zhang Guowei;Xiaoping Wang;Verma, P.R.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Comparison of Wafer-Level With Package-Level CDM Stress Facilitated by Real-Time Probing]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6006519]]></link>
			<description><![CDATA[Using real-time voltage probing and circuit simulation, the stress induced by wafer-level charged-device-model (CDM) electrostatic discharge test methods is compared to that of package-level field-induced CDM testers. It is shown that, while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6006519]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>522</startPage>
			<endPage>530</endPage>
			<fileSize>886</fileSize>
			<authors><![CDATA[Jack, N.;Shukla, V.;Rosenbaum, E.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Temperature Cycling Reliability of High-Temperature Lead-Free Die-Attach Technologies]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=5744108]]></link>
			<description><![CDATA[The demand for electronics capable of operating at temperatures above the traditional 125&#x00B0;C limit continues to increase. Devices based on wide bandgap semiconductors have been demonstrated to operate at temperatures up to 500&#x00B0;C, but packaging remains the major hurdle to product development. Recent regulations, such as RoHS and WEEE, increase the complexity of the packaging task by prohibiting the use of certain materials, such as lead, in electronic products. Traditionally, lead has been widely used in high-temperature solder attach. In this paper, a series of Pb-free die-attach technologies have been identified as possible alternatives to Pb-based ones for high-temperature applications. This paper describes the fabrication sequence for each system and assesses their long-term reliability using accelerated thermal cycling and physics-of-failure modeling. The reliability of the lead-rich alloy was confirmed during this investigation, while early failures of the silver-filled epoxy demonstrated their inability to survive high temperatures. An empirical damage model was developed for the silver nanoparticle paste based on fatigue-induced failures. Encouraging reliability data have been presented for the gold-tin solid-liquid interdiffusion system where bond quality was demonstrated to be a critical factor in its failure mode and mechanism.]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=5744108]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>531</startPage>
			<endPage>539</endPage>
			<fileSize>981</fileSize>
			<authors><![CDATA[Quintero, P.O.;McCluskey, F.P.;]]></authors>
		</item>
		<item>
			<title><![CDATA[The Effects of Al Doping and Metallic-Cap Layers on Electromigration Transport Mechanisms in Copper Nanowires]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6008633]]></link>
			<description><![CDATA[We investigate electromigration transport mechanisms in Cu and Cu alloy damascene conductors. We show that the drift velocity exhibits a dependence on microstructure. We find that Cu-Al alloys exhibit a small increase in grain boundary diffusion activation energy compared to pure Cu and a reduction in the diffusion prefactor for Cu/cap interfacial transport. Cu-silicide- and CoWP-cap layers are both effective in reducing the interfacial component of electromigration primarily through increases in interface diffusion activation energy. The Cu silicide cap also impacts grain boundary electromigration as a result of silicon doping of grain boundaries during processing, while the CoWP cap has no measurable impact on grain boundary transport. The positive impact of Al doping and metallic-cap layers on electromigration is additive, suggesting the potential for impurity doping and metallic caps to be combined to optimize for reliability across the geometry ranges encountered in circuits.]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6008633]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>540</startPage>
			<endPage>547</endPage>
			<fileSize>397</fileSize>
			<authors><![CDATA[Ming-Hsien Lin;Oates, A.S.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Defect Analysis on Optical Waveguide Arrays by Synchrotron Radiation Microtomography]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6022760]]></link>
			<description><![CDATA[In recent years, great attention has been devoted to the study and realization of polymeric optical waveguides embedded in printed circuit boards due to the increasing need of transferring large amounts of data at high speed within computer and telecommunication devices. Nonuniform microstructural defects that can be induced during the manufacturing process can dramatically influence the waveguide performance. The synchrotron radiation computed microtomography technique was used to obtain 3-D microstructural information, specifically to observe small defects, such as porosities, in a nondestructive way. Porosity level and pore size range were evaluated.]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6022760]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>548</startPage>
			<endPage>550</endPage>
			<fileSize>255</fileSize>
			<authors><![CDATA[Manescu, A.;Di Gregorio, G.M.;Girardin, E.;Calbucci, V.;Angeloni, G.;Carta, P.;Giuliani, A.;Albertini, G.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Neutron-Induced Charge Collection Simulation of Bulk FinFET SRAMs Compared With Conventional Planar SRAMs]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6024447]]></link>
			<description><![CDATA[The relative neutron-induced soft-error rate (SER) of bulk FinFET SRAMs compared to planar SRAMs is estimated based on drain area, collected charge, and critical charge using mixed-mode 3-D TCAD simulations. The critical charges of the bulk FinFET and planar devices are comparable, with identical gate length, gate width, and gate oxide thickness. However, the charges collected by the bulk FinFET drain due to ion strikes are smaller than those by the planar FET drain. Bulk FinFETs are anticipated to exhibit lower SER sensitivity compared to planar FETs.]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6024447]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>551</startPage>
			<endPage>554</endPage>
			<fileSize>560</fileSize>
			<authors><![CDATA[Yi-Pin Fang;Oates, A.S.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Thirteenth IEEE International Vacuum Electronics Conference and Ninth IEEE International Vacuum Electron Sources Conference]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094101]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094101]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>555</startPage>
			<endPage>555</endPage>
			<fileSize>1015</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[2012 19th international workshop on active matrix flatpanel displays and devices]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094102]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094102]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>556</startPage>
			<endPage>556</endPage>
			<fileSize>1260</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[2011 Index IEEE Transactions on Device and Materials Reliability Vol. 11]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6095869]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6095869]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>557</startPage>
			<endPage>569</endPage>
			<fileSize>143</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Transactions on Device and Materials Reliability information for authors]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094104]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094104]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>C3</startPage>
			<endPage>C3</endPage>
			<fileSize>29</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[Blank page [back cover]]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094105]]></link>
			<description><![CDATA[This page or pages intentionally left blank.]]></description>
			<pubDate><![CDATA[Dec.  2011]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=6094098&arnumber=6094105]]></guid>
			<volume>11</volume>
			<issue>4</issue>
			<startPage>C4</startPage>
			<endPage>C4</endPage>
			<fileSize>5</fileSize>
			<authors><![CDATA[]]></authors>
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