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		<title><![CDATA[ Semiconductor Manufacturing, IEEE Transactions on - new TOC ]]></title>
		<link>http://ieeexplore.ieee.org</link>
		<description>TOC Alert for Publication# 66 </description>
		<year>2013</year>
		<month>May      </month>
		<day>16</day>
		<item>
			<title><![CDATA[Table of contents]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6512085]]></link>
			<description><![CDATA[Presents the cover/table of contents for this issue of the periodical.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6512085]]></guid>
			<volume>26</volume>
			<issue>2</issue>
			<startPage>C1</startPage>
			<endPage>C1</endPage>
			<fileSize>56</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Transactions on Semiconductor Manufacturing publication information]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6512080]]></link>
			<description><![CDATA[Provides a listing of current staff, committee members and society officers.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6512080]]></guid>
			<volume>26</volume>
			<issue>2</issue>
			<startPage>C2</startPage>
			<endPage>C2</endPage>
			<fileSize>136</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[Best Paper Award and Changes to the Editorial Board]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6512092]]></link>
			<description><![CDATA[The editors chose "Lens Heating Induced Aberration Prediction via Nonlinear Kalman Filters," by Can Bikcora, Martiijn van Veelen, Siep Weiland, and Wim M. J. Coene, as the Best Paper for the Transactions published in 2012.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6512092]]></guid>
			<volume>26</volume>
			<issue>2</issue>
			<startPage>177</startPage>
			<endPage>177</endPage>
			<fileSize>22</fileSize>
			<authors><![CDATA[Cunningham, S.P.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Layered Drum-Buffer-Rope-Based Scheduling of Reentrant Manufacturing Systems]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6470702]]></link>
			<description><![CDATA[Reentrant flow is a phenomenon in which a product revisits several machines multiple times on its production route. A manufacturing system with reentrant flow is well recognized as a highly complex system. Its reentrance feature challenges the scheduling researchers. To cope with this problem, a kind of drum-buffer-rope (DBR) technique proves to be a viable robust method for complex manufacturing system scheduling. This paper investigates DBR-based scheduling for reentrant manufacturing with a novel strategy. First, the multiple reentrant production flow is transferred into nonreentrant layer production lines. Then, the DBR-based scheduling algorithm is studied, and a layered scheduling algorithm (LSA) and the extended LSA are proposed. The proposed layered DBR-based scheduling strategy and the algorithms are demonstrated via a case study. They significantly outperform some commonly used policies in terms of such performance measures as mean cycle time, work-in-process, and equipment utilization ratios.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6470702]]></guid>
			<volume>26</volume>
			<issue>2</issue>
			<startPage>178</startPage>
			<endPage>187</endPage>
			<fileSize>695</fileSize>
			<authors><![CDATA[Qiao, F.;Wu, Q.;]]></authors>
		</item>
		<item>
			<title><![CDATA[A Literature Review on Sampling Techniques in Semiconductor Manufacturing]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6494322]]></link>
			<description><![CDATA[This paper reviews sampling techniques for inspection in semiconductor manufacturing. We discuss the strengths and weaknesses of techniques developed in the last last 20 years for excursion monitoring (when a process or machine falls out of specifications) and control. Sampling techniques are classified into three main groups: static, adaptive, and dynamic. For each group, a classification is performed per year, approach, and industrial deployment. A comparison between the groups indicates a complementarity strongly linked to the semiconductor environment. Benefits and drawbacks of each group are discussed, showing significant improvements from static to dynamic through adaptive sampling techniques. Dynamic sampling seems to be more appropriate for modern semiconductor plants.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6494322]]></guid>
			<volume>26</volume>
			<issue>2</issue>
			<startPage>188</startPage>
			<endPage>195</endPage>
			<fileSize>93</fileSize>
			<authors><![CDATA[Nduhura-Munga, J.;Rodriguez-Verjan, G.;Dauzere-Peres, S.;Yugma, C.;Vialletelle, P.;Pinaton, J.;]]></authors>
		</item>
		<item>
			<title><![CDATA[A Survey of Yield Modeling and Yield Enhancement Methods]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6423953]]></link>
			<description><![CDATA[Fast yield learning is critical to bringing products to the market in a timely fashion and is strongly linked to product revenues. This paper reviews methods to enable efficient yield learning, focusing on methods to quantify the most significant yield detractors and on in-line excursion detection methodologies.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6423953]]></guid>
			<volume>26</volume>
			<issue>2</issue>
			<startPage>196</startPage>
			<endPage>213</endPage>
			<fileSize>556</fileSize>
			<authors><![CDATA[Milor, L.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Removal of Tetramethylammonium Hydroxide From Solution Using Ion Exchange]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6459044]]></link>
			<description><![CDATA[Ion exchange is used to remove tetramethylammonium hydroxide from an aqueous solution. Both strong acid cation (SAC) and weak acid cation (WAC) exchange resins show excellent uptake of the <formula formulatype="inline"><tex Notation="TeX">${rm TMA}^{+}$</tex></formula> ion. The pseudo-second-order kinetic model fits the data of uptake rate well. When using an SAC exchange resin, the pH does not affect the uptake efficiency, while that of the WAC exchange resin is strongly affected by the pH. Regeneration experiments show excellent performance of resins after five cycles. The selectivity coefficient of <formula formulatype="inline"><tex Notation="TeX">${rm TMA}^{+}$</tex></formula> over <formula formulatype="inline"><tex Notation="TeX">${rm H}^{+}$</tex></formula> for SAC is calculated as 5.16, while for WAC, in the bulk solution, the selectivity coefficient is notably lower <formula formulatype="inline"><tex Notation="TeX">$(6.45times 10^{-4})$</tex></formula>. The presence of competing ions interfere with the <formula formulatype="inline"><tex Notation="TeX">${rm TMA}^{+}$</tex></formula> uptake, of which <formula formulatype="inline"><tex Notation="TeX">${rm Mg}^{2+}$</tex></formula> has the most notable effect. The ion exchange model is applied to obtain resin selectivity over the <formula formulatype="inline"><tex Notation="TeX">${rm TMA}^{+}$</tex></formula> ion as well.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6459044]]></guid>
			<volume>26</volume>
			<issue>2</issue>
			<startPage>214</startPage>
			<endPage>220</endPage>
			<fileSize>321</fileSize>
			<authors><![CDATA[Citraningrum, H.M.;Liu, J.C.;Chern, J.M.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Design and Fabrication of a Horn-Type Megasonic Waveguide for Nanoparticle Cleaning]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6407941]]></link>
			<description><![CDATA[In this article, finite element analysis and fabrication of a horn-type megasonic waveguide for nanoparticle cleaning is carried out. To design the megasonic system, the impedance graph of the megasonic waveguide is analyzed using the finite element method software ANSYS. The predicted antiresonance frequency of the piezoelectric actuator used in the system is 1003 kHz, which agrees well with the measured value of a manufactured piezoelectric actuator 1005 kHz. In addition, the antiresonance frequency of a quartz waveguide with the lead zirconate titanate actuator is predicted as 1001 kHz, which also agrees well with the experimental data of 1003 kHz. Acoustic analysis to predict the acoustic pressure distribution of the waveguide is performed, and well distributed pressures in water is observed at the end of the waveguide. Also, the acoustic pressure of the developed quartz waveguide is measured and compared with that of a commercial megasonic system having 1 MHz operating frequency. The quartz waveguide system provides a 25% more acoustic pressure output. In addition, the standard deviation is decreased by 27%. Finally, a particle removal efficiency test shows over 91% particle removal after cleaning. These results suggest that the horn-type megasonic waveguide can be applied to the nanoparticle cleaning process.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6407941]]></guid>
			<volume>26</volume>
			<issue>2</issue>
			<startPage>221</startPage>
			<endPage>225</endPage>
			<fileSize>729</fileSize>
			<authors><![CDATA[Kim, H.;Lee, Y.;Lim, E.;]]></authors>
		</item>
		<item>
			<title><![CDATA[A Precision Mismatch Measurement Technique for Integrated Capacitor Array Using a Switched Capacitor Amplifier]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6488873]]></link>
			<description><![CDATA[This paper presents a precision mismatch measurement method to characterize an integrated capacitor array. Conventional mismatch measurement methods using floating gate capacitance measurement (FGCM) have measurement error due to the large input-referred noise and the small input signal range of the source follower. In order to improve the measurement accuracy, we propose a new measurement method using a parasitic-insensitive switched capacitor amplifier and the correlated double sampling (CDS) technique. The CDS technique eliminates the measurement error from parasitic capacitances, switching errors, and the offset voltage of the amplifier. In order to verify the proposed method, a test chip was fabricated using a 0.18-<formula formulatype="inline"> <tex Notation="TeX">${mmb{mu}}{rm m}$</tex></formula> CMOS process. The chip consists of a 4<formula formulatype="inline"> <tex Notation="TeX">$,times,$</tex></formula>16 metal&#x2013;insulator&#x2013;metal capacitor array and a measurement circuit. The measured standard deviation of the capacitance mismatch, <formula formulatype="inline"><tex Notation="TeX">$sigma(Delta{rm C}_{n}{{&lt;}{rm C}{&#x003E;}})$</tex></formula>, ranges from 0.0067% to 0.0130%, and the measured standard deviation of the short-term repeatability, <formula formulatype="inline"><tex Notation="TeX">$sigma(Delta (Delta{rm C}_{n}/{&lt;}{rm C}{&#x003E;}))$</tex></formula>, is 0.0025%. These results show that the measurement accuracy of the proposed method is improved by ten times over that of the FGCM method.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6488873]]></guid>
			<volume>26</volume>
			<issue>2</issue>
			<startPage>226</startPage>
			<endPage>232</endPage>
			<fileSize>982</fileSize>
			<authors><![CDATA[Kwon, Y.-C.;Kwon, O.-K.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Design and Fabrication of Si-Diaphragm, ZnO Piezoelectric Film-Based MEMS Acoustic Sensor Using SOI Wafers]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6410046]]></link>
			<description><![CDATA[This paper reports a simpler technique for fabricating an microelectromechanical system acoustic sensor based on a piezoelectric zinc oxide (ZnO) thin film, utilizing silicon-on-insulator wafers. A highly <formula formulatype="inline"><tex Notation="TeX">$c$</tex></formula>-axis-oriented ZnO film of thickness 2.4 <formula formulatype="inline"><tex Notation="TeX">$mu{rm m}$</tex></formula>, which is covered with 0.2-<formula formulatype="inline"><tex Notation="TeX">$mu{rm m}$</tex></formula>-thick PECVD <formula formulatype="inline"><tex Notation="TeX">${rm SiO}_{2}$</tex></formula>, is sandwiched between two aluminum electrodes on a 25-<formula formulatype="inline"> <tex Notation="TeX">$mu{rm m}$</tex></formula>-thick silicon diaphragm. This diaphragm thickness has been optimized to withstand sound pressure level range of 120&#x2013;160 dB. Stress distribution studies using ANSYS have been performed to determine the locations for placement of capacitor electrodes. This paper also reports a technique for the creation of a positive slope of the ZnO step to ensure proper coverage during Al metallization. In order to maximize yield, process steps have been developed to avoid the microtunnel blockage by silicon/glass particles. The packaged sensor is found to exhibit a sensitivity of 382 <formula formulatype="inline"><tex Notation="TeX">$mu{rm V/Pa}$</tex></formula> (RMS) in the frequency range from 30 to 8000 Hz, under varying acoustic pressure.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6410046]]></guid>
			<volume>26</volume>
			<issue>2</issue>
			<startPage>233</startPage>
			<endPage>241</endPage>
			<fileSize>868</fileSize>
			<authors><![CDATA[Prasad, M.;Sahula, V.;Khanna, V.K.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Multi-Function Thermopile Sensors Fabricated With a MEMS-Compatible Process]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6481460]]></link>
			<description><![CDATA[In this paper, we present micromachined multifunction thermopile sensors based on the Seebeck effect. A single sensor is able to perform measurement on temperature, pressure, humidity, and percentage of a gas constituent. Three different designs are employed and compared.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6481460]]></guid>
			<volume>26</volume>
			<issue>2</issue>
			<startPage>242</startPage>
			<endPage>247</endPage>
			<fileSize>974</fileSize>
			<authors><![CDATA[Sin, L.-M.;Pan, T.-T.;Tsai, C.-W.;Chou, C.-F.;Hong, J.-Q.;Tsai, J.-C.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Improving Breakdown Voltage of LDMOS Using a Novel Cost Effective Design]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502737]]></link>
			<description><![CDATA[A reduced surface field (RESURF) laterally diffused metal oxide semiconductor (LDMOS) device with the concept of charge compensation using p-implant layer (PIL) without additional process step is proposed in standard 0.18-<formula formulatype="inline"><tex Notation="TeX">$mu{rm m}$</tex></formula> technology. By simply using the p-type drift drain (PDD) implantation of p-type LDMOS into n-type LDMOS, breakdown voltage <formula formulatype="inline"><tex Notation="TeX">$({rm V_{BD}})$</tex></formula> is substantially improved. For a thorough study of device phenomena, hydrodynamic transport simulations are first performed to analyze the electric field distributions at high voltage bias in order to explain increases in breakdown voltage and predict its optimal design parameter. Then fabrication of the devices is performed and shows that the breakdown voltages increase significantly. The measurement results show a 12% improvement in <formula formulatype="inline"><tex Notation="TeX">${rm V}_{rm BD}$</tex></formula> and a 5% improvement in figure of merit (FOM). Throughout the fabrication process, the enlarged breakdown voltage obtained by the PIL without additional process and device area show the potential of cost effective. Because such devices have good off-state breakdown voltage and specific on-resistance, they are very competitive with similar technologies and promising system-on-chip (SOC) applications.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502737]]></guid>
			<volume>26</volume>
			<issue>2</issue>
			<startPage>248</startPage>
			<endPage>252</endPage>
			<fileSize>506</fileSize>
			<authors><![CDATA[Han, M.-H.;Chen, H.-B.;Chang, C.-J.;Tsai, C.-C.;Chang, C.-Y.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Inline-Characterization and Step Coverage Optimization of Deposited Dielectrics in DRAM Structures]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6478839]]></link>
			<description><![CDATA[A combination of a common ellipsometric thickness determination from a plane surface and volume-related information gained from a Fourier transform infrared measurement enables monitoring of thin nm-scale layers in 3-D structures. This method was established to characterize dielectric layers deposited by atomic layer deposition within a capacitor structure of a 65-nm DRAM technology. The influence of precursor flow and pulse time on the overall homogeneity and step coverage of zirconium aluminum oxide was investigated. A clear correlation to the precursor amount and the geometry of the deposition tool can be shown.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6478839]]></guid>
			<volume>26</volume>
			<issue>2</issue>
			<startPage>253</startPage>
			<endPage>259</endPage>
			<fileSize>771</fileSize>
			<authors><![CDATA[Krupinski, M.;Kasic, A.;Hecht, T.;Klude, M.;Heitmann, J.;Erben, E.;Mikolajick, T.;]]></authors>
		</item>
		<item>
			<title><![CDATA[2013 International Electron Devices Meeting]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6512075]]></link>
			<description><![CDATA[Describes the above-named upcoming conference event. May include topics to be covered or calls for papers.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6512075]]></guid>
			<volume>26</volume>
			<issue>2</issue>
			<startPage>260</startPage>
			<endPage>260</endPage>
			<fileSize>338</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Transactions on Semiconductor Manufacturing information for authors]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6512087]]></link>
			<description><![CDATA[Provides instructions and guidelines to prospective authors who wish to submit manuscripts.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6512087]]></guid>
			<volume>26</volume>
			<issue>2</issue>
			<startPage>C3</startPage>
			<endPage>C3</endPage>
			<fileSize>95</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[[Blank page - back cover]]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6512077]]></link>
			<description><![CDATA[??This page or pages intentionally left blank.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6512077]]></guid>
			<volume>26</volume>
			<issue>2</issue>
			<startPage>C4</startPage>
			<endPage>C4</endPage>
			<fileSize>5</fileSize>
			<authors><![CDATA[]]></authors>
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