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		<title><![CDATA[ Power Electronics, IEEE Transactions on - new TOC ]]></title>
		<link>http://ieeexplore.ieee.org</link>
		<description>TOC Alert for Publication# 63 </description>
		<year>2013</year>
		<month>May      </month>
		<day>16</day>
		<item>
			<title><![CDATA[Table of Contents]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514770]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514770]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>C1</startPage>
			<endPage>4866</endPage>
			<fileSize>129</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Transactions on Power Electronics publication information]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514544]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514544]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>C2</startPage>
			<endPage>C2</endPage>
			<fileSize>131</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[Fault Detection for Modular Multilevel Converters Based on Sliding Mode Observer]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6418042]]></link>
			<description><![CDATA[This letter presents a fault detection method for modular multilevel converters which is capable of locating a faulty semiconductor switching device in the circuit. The proposed fault detection method is based on a sliding mode observer (SMO) and a switching model of a half-bridge, the approach taken is to conjecture the location of fault, modify the SMO accordingly and then compare the observed and measured states to verify, or otherwise, the assumption. This technique requires no additional measurement elements and can easily be implemented in a DSP or microcontroller. The operation and robustness of the fault detection technique are confirmed by simulation results for the fault condition of a semiconductor switching device appearing as an open circuit.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6418042]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>4867</startPage>
			<endPage>4872</endPage>
			<fileSize>842</fileSize>
			<authors><![CDATA[Shao, S.;Wheeler, P.W.;Clare, J.C.;Watson, A.J.;]]></authors>
		</item>
		<item>
			<title><![CDATA[An Inner Current Suppressing Method for Modular Multilevel Converters]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6418040]]></link>
			<description><![CDATA[Ideally, the inner (the upper or lower arm) current of a modular multilevel converter (MMC) is ideally assumed to be the sum of a dc component and an ac component of the fundamental frequency. However, as ac current flows through the submodule (SM) capacitors, the capacitor voltages fluctuate with time. Consequently, the inner current is usually distorted and the peak/RMS value of it is increased compared with the theoretical value. The increased currents will increase power losses and may threaten the safe operation of the power devices and capacitors. This paper proposes a closed-loop method for suppression of the inner current in an MMC. This method is very simple and is implemented in a stationary frame, and no harmonic extraction algorithm is needed. Hence, it can be applied to single-phase or three-phase MMCs. Besides, this method does not influence the balancing of the SM capacitor voltages. Simulation and experimental results show that the proposed method can suppress the peak and RMS values of the inner currents dramatically.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6418040]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>4873</startPage>
			<endPage>4879</endPage>
			<fileSize>943</fileSize>
			<authors><![CDATA[Li, Z.;Wang, P.;Chu, Z.;Zhu, H.;Luo, Y.;Li, Y.;]]></authors>
		</item>
		<item>
			<title><![CDATA[&#x0393;-Z-Source Inverters]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6423940]]></link>
			<description><![CDATA[Voltage-type &#x0393;-Z-source inverters are proposed in this letter. They use a unique &#x0393;-shaped impedance network for boosting their output voltage in addition to their usual voltage-buck behavior. Comparing them with other topologies, the proposed inverters use lesser components and a coupled transformer for producing the high-gain and modulation ratio simultaneously. The obtained gain can be tuned by varying the turns ratio <formula formulatype="inline"><tex Notation="TeX">$gamma _{Gamma Z} $</tex></formula> of the transformer within the narrow range of <formula formulatype="inline"><tex Notation="TeX">$1 &lt; gamma _{Gamma Z} le 2$</tex></formula>. This leads to lesser winding turns at high gain, as compared to other related topologies. Experimental testing has already proven the validity of the proposed inverters.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6423940]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>4880</startPage>
			<endPage>4884</endPage>
			<fileSize>794</fileSize>
			<authors><![CDATA[Loh, P.C.;Li, D.;Blaabjerg, F.;]]></authors>
		</item>
		<item>
			<title><![CDATA[An Improved Soft-Switching Buck Converter With Coupled Inductor]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6419844]]></link>
			<description><![CDATA[This letter presents a novel topology for a buck dc&#x2013;dc converter with soft-switching capability, which operates under a zero-current-switching condition at turn on and a zero-voltage-switching condition at turn off. In order to realize soft switching, based on a basic buck converter, the proposed converter added a small inductor, a diode, and an inductor coupled with the main inductor. Because of soft switching, the proposed converter can obtain a high efficiency under heavy load conditions. Moreover, a high efficiency is also achieved under light load conditions, which is significantly different from other soft-switching buck converters. The detailed theoretical analyses of steady-state operation modes are presented, and the detailed design methods and some simulation results are also given. Finally, a 600&#x00A0;W prototype is built to validate the theoretical principles. The switching waveforms and the efficiencies are also measured to validate the proposed topology.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6419844]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>4885</startPage>
			<endPage>4891</endPage>
			<fileSize>564</fileSize>
			<authors><![CDATA[Jiang, L.;Mi, C.C.;Li, S.;Yin, C.;Li, J.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Quasi-Resonant Boost-Half-Bridge Converter With Reduced Turn-Off Switching Losses for 16&#x00A0;V Fuel Cell Application]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6422401]]></link>
			<description><![CDATA[An active-clamped current-fed converter can achieve not only lossless clamping but also zero-voltage switching. In particular, a boost-half-bridge (BHB) converter is one of the most suitable candidates for high-current, high-step-up applications owing to its low transformer turn ratio, reduced voltage rating of diodes, zero magnetizing dc offset, and symmetrical structure for all components. In this letter a quasi-resonant switching technique for a BHB converter with active clamping is proposed to significantly reduce turn-off switching losses. Experimental results for a 16&#x00A0;V, 1.2 kW prototype validate the effectiveness of the proposed concept.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6422401]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>4892</startPage>
			<endPage>4896</endPage>
			<fileSize>883</fileSize>
			<authors><![CDATA[Park, C.;Choi, S.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Soft-Switched Dual-Input DC&#x2013;DC Converter Combining a Boost-Half-Bridge Cell and a Voltage-Fed Full-Bridge Cell]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6468112]]></link>
			<description><![CDATA[This letter presents a new zero-voltage-switching (ZVS) isolated dc&#x2013;dc converter which combines a boost half-bridge (BHB) cell and a full-bridge (FB) cell, so that two different type of power sources, i.e., both current fed and voltage fed, can be coupled effectively by the proposed converter for various applications, such as fuel cell and supercapacitor hybrid energy system. By fully using two high- frequency transformers and a shared leg of switches, number of the power devices and associated gate driver circuits can be reduced. With phase-shift control, the converter can achieve ZVS turn-on of active switches and zero-current switching (ZCS) turn-off of diodes. In this letter, derivation, analysis, and design of the proposed converter are presented. Finally, a 25&#x2013;50&#x00A0;V input, 300&#x2013;400&#x00A0;V output prototype with a 600&#x00A0;W nominal power rating is built up and tested to demonstrate the effectiveness of the proposed converter topology.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6468112]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>4897</startPage>
			<endPage>4902</endPage>
			<fileSize>5788</fileSize>
			<authors><![CDATA[Zhang, Z.;Thomsen, O.C.;Andersen, M.A.E.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Accelerated Simulation of High-Fidelity Models of Supercapacitors Using Waveform Relaxation Techniques]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6472321]]></link>
			<description><![CDATA[The waveform relaxation (WR) technique is used to accelerate the time-domain simulation of high-fidelity models of supercapacitors. Because of their high power density, supercapacitors are suitable energy storage options in electrified transportation fleets and renewable energy systems. Given their fast charging/discharging profile, high-fidelity models, such as transmission-line models or multistage ladder structures, are conventionally adopted for design and simulation purposes. High-fidelity models, that include fast dynamic modes, can slow down the simulation process. This is problematic, in particular, since supercapacitors are parts of a larger, more complex system, e.g., a power train, with a wide dynamic range. In this paper, frequency-domain characterization of a supercapacitor is conducted by the electrochemical impedance spectroscopy. Then, the equivalent multistage ladder model of the supercapacitor is extracted and parameterized. The high-fidelity model is verified by considering the measured charging profile of the supercapacitor. The WR technique, including circuit partitioning and time windowing, is considered for the resulting high-fidelity model. WR results in an order-of-magnitude improvement in simulation speed while maintaining an excellent agreement with the hardware measurement and conventional simulations.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6472321]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>4903</startPage>
			<endPage>4909</endPage>
			<fileSize>1346</fileSize>
			<authors><![CDATA[Moayedi, S.;Cingoz, F.;Davoudi, A.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Nonlinear Current Control for Power Electronic Converters: IC Design Aspects and Implementation]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6466391]]></link>
			<description><![CDATA[This letter provides design guidelines and presents a fully integrated implementation of the recently proposed nonlinear average current control (NACC) algorithm for power factor correction and dc&#x2013;dc converters. The control performance and dynamics of the current-mode controlled power electronic converter strongly depends on the accuracy of the applied current sensing method. Several current sensing methods have been proposed in the literature, including the senseFET method, which is suitable for on-chip current measurement. This letter presents a modification of the senseFET on-chip current sensing technique dedicated for an ultrahigh sensing ratio and suited for the current sensing processing, which gives current-type output what fits well with the NACC control method, thus further simplifying the converter design and reducing cost as well as noise sensitivity of the control circuitry. Hence, the need for a voltage-to-current and current-to-voltage transformation circuit is eliminated. Therefore, the proposed method of the current sensing is applicable to any boost-like converter, whose control system requires an extremely high sensing ratio to be achieved. Nevertheless, it is especially well suited to be combined with an NACC control circuitry irrespective of the required sensing ratio. Experimental results verify the proposed design done in 0.35-&#x03BC;m HV triple-well CMOS technology.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6466391]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>4910</startPage>
			<endPage>4916</endPage>
			<fileSize>1638</fileSize>
			<authors><![CDATA[Nikolic, M.;Enne, R.;Goll, B.;Zimmermann, H.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Enhancement of Commutation Reliability of an HVDC Inverter by Means of an Inductive Filtering Method]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6513268]]></link>
			<description><![CDATA[A new filter-commutated inverter (FCI) is proposed in this paper to enhance the commutation reliability of the HVDC systems applied in the high-voltage fields. The topology of the FCI is established based on an inductive filtering method, which mainly consists of a new converter transformer, fully tuned (FT) branches, inverter bridges, and a related control system. Unlike the traditional line-commutated inverter (LCI), the equivalent commutating impedance of the FCI includes not only the transformer leakage impedance but also the total impedance of the FT branches. The mathematical model is established to express such equivalent commutating impedance. Based on this, the commutation performance of the FCI is investigated in detail by comparing with LCI. Besides, the commutation reliability is evaluated under different operating conditions (e.g., normal operation, balanced, and unbalanced faults). Both the simulation and the experimental results validate the theoretical analysis, and indicate that the FCI with the use of the inductive filtering method can greatly increase the commutation margin of the HVDC systems, enhance the commutation reliability of the inverter, and prevent the occurrence of commutation failures.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6513268]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>4917</startPage>
			<endPage>4929</endPage>
			<fileSize>1539</fileSize>
			<authors><![CDATA[Li, Y.;Liu, F.;Luo, L.;Rehtanz, C.;Cao, Y.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Cascaded Multilevel Converter-Based Transmission STATCOM: System Design Methodology and Development of a 12 kV &#x00B1;12 MVAr Power Stage]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6410044]]></link>
			<description><![CDATA[This paper deals with the design methodology for cascaded multilevel converter (CMC)-based transmission-type STATCOM (T-STATCOM) and the development of a &#x00B1;12 MVAR, 12&#x00A0;kV line-to-line wye-connected, 11-level CMC. Sizing of the CMC module, the number of H-bridges (HBs) in each phase of the CMC, ac voltage rating of the CMC, the number of paralleled CMC modules in the T-STATCOM system, the optimum value of series filter reactors, and the determination of busbar in the power grid to which the T-STATCOM system is going to be connected are also discussed in this paper in view of the IEEE Std. 519-1992, current status of high voltage (HV) insulated gate bipolar transistor (IGBT) technology, and the required reactive power variation range for the T-STATCOM application. In the field prototype of the CMC module, the ac voltages are approximated to sinusoidal waves by the selective harmonic elimination method (SHEM). The equalization of dc-link capacitor voltages is achieved according to the modified selective swapping (MSS) algorithm. In this study, an L-shaped laminated bus has been designed and the HV IGBT driver circuit has been modified for the optimum switching performance of HV IGBT modules in each HB. The laboratory and field performances of the CMC module and of the resulting T-STATCOM system are found to be satisfactory and quite consistent with the design objectives.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6410044]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>4930</startPage>
			<endPage>4950</endPage>
			<fileSize>3169</fileSize>
			<authors><![CDATA[Gultekin, B.;Ermis, M.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Variable Switching Frequency PWM for Three-Phase Converters Based on Current Ripple Prediction]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6418039]]></link>
			<description><![CDATA[Compared with the widely used constant switching frequency pulse-width-modulation (PWM) method, variable switching frequency PWM can benefit more because of the extra freedom. Based on the analytical expression of current ripple of three-phase converters, variable switching frequency control methods are proposed to satisfy different ripple requirements. Switching cycle <formula formulatype="inline"><tex Notation="TeX">$T_{s}$</tex></formula> is updated in DSP in every interruption period based on the ripple requirement. Two methods are discussed in this paper. The first method is designed to arrange the current ripple peak value within a certain value and can reduce the equivalent switching frequency and electromagnetic interference (EMI) noise; the second method is designed to keep ripple current RMS value constant and reduce the EMI noise. Simulation and experimental results show that variable switching frequency control could improve the performance of EMI and efficiency without impairing the power quality.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6418039]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>4951</startPage>
			<endPage>4961</endPage>
			<fileSize>1500</fileSize>
			<authors><![CDATA[Jiang, D.;Wang, F.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Isolated Three-Phase High Power Factor Rectifier Based on the SEPIC Converter Operating in Discontinuous Conduction Mode]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6464604]]></link>
			<description><![CDATA[This paper presents the analysis and design of a three-phase high power factor rectifier, based on the dc&#x2013;dc single-ended primary-inductance converter (SEPIC) operating in discontinuous conduction mode, with output voltage regulation and high frequency isolation. The input high power factor is naturally attained through the operational mode without the use of current sensors and a current control loop. To validate the theoretical analysis, a design example and experimental results for a 4-kW, 380-V line-to-line input voltage, 400-V output voltage, 0.998 power factor, 40-kHz switching frequency, and 4&#x0025; input current total harmonic distortion laboratory prototype are presented, considering two distinct modulators. In addition, experimental results for the output voltage closed-loop control are presented.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6464604]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>4962</startPage>
			<endPage>4969</endPage>
			<fileSize>2058</fileSize>
			<authors><![CDATA[Tibola, G.;Barbi, I.;]]></authors>
		</item>
		<item>
			<title><![CDATA[CCTT-Core Split-Winding Integrated Magnetic for High-Power DC&#x2013;DC Converters]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6412807]]></link>
			<description><![CDATA[A novel CCTT-core split-winding integrated magnetic (IM) structure is presented in this paper. The IM device is optimized for use in high-power dc&#x2013;dc converters. The IM structure uses a split-winding configuration which allows for the reduction of external leakage inductance, which is a problem for many IM designs. Magnetic poles are incorporated to help shape and contain the leakage flux within the core window. Low-cost and low-power loss ferrite is used which results in a very efficient design. An IM reluctance model is developed which uses fringing equations to develop a more accurate design. An IM design algorithm is developed and implemented in Mathematica for design and optimization. FEA and experimental results from a 72 kW, (155-V dc, 465-A dc input, and 420-V dc output) prototype validate the new IM concept. The 72 kW CCTT- core IM was shown to be 99.7&#x0025; efficient at full load.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6412807]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>4970</startPage>
			<endPage>4984</endPage>
			<fileSize>2031</fileSize>
			<authors><![CDATA[Hartnett, K.J.;Hayes, J.G.;Egan, M.G.;Rylko, M.S.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Advantages and Challenges of a Type-3 PLL]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6412806]]></link>
			<description><![CDATA[A phase-locked loop (PLL) is a closed-loop feedback control system, which synchronizes its output signal in frequency as well as in phase with an input signal. The phase detector, the loop filter, and the voltage controlled oscillator are the key parts of almost all PLLs. Within the areas of power electronics and power systems, which are focused on in this paper, the PLLs typically employ a proportional-integral controller as the loop filter, resulting in a type-2 control system (a control system of type-N has N poles at the origin in its open-loop transfer function). Recently, some attempts have been made to design type-3 PLLs, either by employing a specific second-order controller as the loop filter, or by implementing two parallel tracking paths for the PLL. For this type of PLLs, however, the advantages and limitations are not clear at all, as the results reported in different literature are contradictory, and there is no detailed knowledge about their stability and dynamic characteristics. In this paper, different approaches to realize a type-3 PLL are examined first. Then, a detailed study of dynamics and analysis of stability, followed by comprehensive parameters design guidelines for a typical type-3 PLL are presented. Finally, to get insight into the advantages/limitations of this type of PLLs, the performance of a well-tuned type-3 PLL is compared with a conventional synchronous reference frame PLL (which is a type-2 PLL) through extensive experimental results and some theoretical discussions.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6412806]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>4985</startPage>
			<endPage>4997</endPage>
			<fileSize>1783</fileSize>
			<authors><![CDATA[Golestan, S.;Monfared, M.;Freijedo, F.D.;Guerrero, J.M.;]]></authors>
		</item>
		<item>
			<title><![CDATA[A Novel RPV (Reactive-Power-Variation) Antiislanding Method Based on Adapted Reactive Power Perturbation]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6461421]]></link>
			<description><![CDATA[In this paper, a novel intermittent reactive-power-variation (RPV) method based on loads&#x2019; resonance frequency detection is proposed to reduce the injected reactive power. The RPV method detects the frequency of point of common coupling (PCC) and outputs the minimum reactive variation, which perturbs the frequency of PCC to the frequency thresholds decided by the utility standards when the islanding condition happens. Furthermore, the islanding detecting control strategy under unbalanced loads condition is discussed. Compared with the traditional bilateral RPV method, the proposed method only output unilateral RPV in each variation period and the variation amplitude of each period is less than 5&#x0025; of the output active power <formula formulatype="inline"><tex Notation="TeX">$(P)$ </tex></formula>, thus the perturbation of reactive power can be reduced significantly. In addition, experimental results of a three-phase 30-kW inverter are given to verify the proposed method. The proposed method is proved to be capable of islanding detection with balanced loads, motor loads within standard permissible detection times. The application of the proposed method to unbalanced loads is also discussed.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6461421]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>4998</startPage>
			<endPage>5012</endPage>
			<fileSize>1946</fileSize>
			<authors><![CDATA[Zhu, Y.;Xu, D.;He, N.;Ma, J.;Zhang, J.;Zhang, Y.;Shen, G.;Hu, C.;]]></authors>
		</item>
		<item>
			<title><![CDATA[New Random PWM Technique for a Full-Bridge DC/DC Converter With Harmonics Intensity Reduction and Considering Efficiency]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6412804]]></link>
			<description><![CDATA[PWM techniques for a full-bridge dc/dc converter are investigated and a new random PWM technique is proposed in this paper. Three PWM techniques with constant switching frequency are discussed and the related random PWM techniques which spread the harmonic clusters and give constant average inductor current to reduce the output voltage ripple are discussed. The pros and cons of three constant switching frequency PWM techniques and the related random counterparts are investigated. Experimental results show that there is a significant efficiency drop of the random PWM technique due to significant increase of switching counts. Therefore, this paper presents a new random PWM technique to significantly reduce the harmonic intensity while not causing relevant impact on the efficiency. An FPGA-based digital-controlled isolated full-bridge dc/dc converter prototype is built to verify the performance of conventional and proposed PWM techniques. The specifications of the converter include the following: input voltage &#x003D; 400&#x00A0;V, output voltage &#x003D; 12&#x00A0;V, output power &#x003D; 528&#x00A0;W, and switching frequency &#x003D; 100&#x00A0;kHz. Measured efficiency and harmonic spread factor will be used for the evaluation of these PWM techniques.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6412804]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5013</startPage>
			<endPage>5023</endPage>
			<fileSize>1566</fileSize>
			<authors><![CDATA[Lai, Y.-S.;Chen, B.-Y.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Mitigation of Lower Order Harmonics in a Grid-Connected Single-Phase PV Inverter]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6408380]]></link>
			<description><![CDATA[In this paper, a simple single-phase grid-connected photovoltaic (PV) inverter topology consisting of a boost section, a low-voltage single-phase inverter with an inductive filter, and a step-up transformer interfacing the grid is considered. Ideally, this topology will not inject any lower order harmonics into the grid due to high-frequency pulse width modulation operation. However, the nonideal factors in the system such as core saturation-induced distorted magnetizing current of the transformer and the dead time of the inverter, etc., contribute to a significant amount of lower order harmonics in the grid current. A novel design of inverter current control that mitigates lower order harmonics is presented in this paper. An adaptive harmonic compensation technique and its design are proposed for the lower order harmonic compensation. In addition, a proportional-resonant-integral (PRI) controller and its design are also proposed. This controller eliminates the dc component in the control system, which introduces even harmonics in the grid current in the topology considered. The dynamics of the system due to the interaction between the PRI controller and the adaptive compensation scheme is also analyzed. The complete design has been validated with experimental results and good agreement with theoretical analysis of the overall system is observed.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6408380]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5024</startPage>
			<endPage>5037</endPage>
			<fileSize>2036</fileSize>
			<authors><![CDATA[Kulkarni, A.;John, V.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Adaptive Voltage Control of the DC/DC Boost Stage in PV Converters With Small Input Capacitor]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6414653]]></link>
			<description><![CDATA[In the case of photovoltaic (PV) systems, an adequate PV voltage regulation is fundamental in order to both maximize and limit the power. For this purpose, a large input capacitor has traditionally been used. However, when reducing that capacitor&#x0027;s size, the nonlinearities of the PV array make the performance of the voltage regulation become highly dependent on the operating point. This paper analyzes the nonlinear characteristics of the PV generator and clearly states their effect on the control of the dc/dc boost stage of commercial converters by means of a linearization around the operating point. Then, it proposes an adaptive control, which enables the use of a small input capacitor preserving at the same time the performance of the original system with a large capacitor. Experimental results are carried out for a commercial converter with a 40&#x00A0;&#x03BC;F input capacitor, and a 4 kW PV array. The results corroborate the theoretical analysis; they evidence the problems of the traditional control, and validate the proposed control with such a small capacitor.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6414653]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5038</startPage>
			<endPage>5048</endPage>
			<fileSize>1129</fileSize>
			<authors><![CDATA[Urtasun, A.;Sanchis, P.;Marroyo, L.;]]></authors>
		</item>
		<item>
			<title><![CDATA[A High Step-Up Three-Port DC&#x2013;DC Converter for Stand-Alone PV/Battery Power Systems]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6422400]]></link>
			<description><![CDATA[A three-port dc&#x2013;dc converter integrating photovoltaic (PV) and battery power for high step-up applications is proposed in this paper. The topology includes five power switches, two coupled inductors, and two active-clamp circuits. The coupled inductors are used to achieve high step-up voltage gain and to reduce the voltage stress of input side switches. Two sets of active-clamp circuits are used to recycle the energy stored in the leakage inductors and to improve the system efficiency. The operation mode does not need to be changed when a transition between charging and discharging occurs. Moreover, tracking maximum power point of the PV source and regulating the output voltage can be operated simultaneously during charging/discharging transitions. As long as the sun irradiation level is not too low, the maximum power point tracking (MPPT) algorithm will be disabled only when the battery charging voltage is too high. Therefore, the control scheme of the proposed converter provides maximum utilization of PV power most of the time. As a result, the proposed converter has merits of high boosting level, reduced number of devices, and simple control strategy. Experimental results of a 200-W laboratory prototype are presented to verify the performance of the proposed three-port converter.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6422400]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5049</startPage>
			<endPage>5062</endPage>
			<fileSize>2171</fileSize>
			<authors><![CDATA[Chen, Y.-M.;Huang, A.Q.;Yu, X.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Modular Multilevel Inverter with New Modulation Method and Its Application to Photovoltaic Grid-Connected Generator]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6428710]]></link>
			<description><![CDATA[This paper proposed an improved phase disposition pulse width modulation (PDPWM) for a modular multilevel inverter which is used for Photovoltaic grid connection. This new modulation method is based on selective virtual loop mapping, to achieve dynamic capacitor voltage balance without the help of an extra compensation signal. The concept of virtual submodule (VSM) is first established, and by changing the loop mapping relationships between the VSMs and the real submodules, the voltages of the upper/lower arm&#x0027;s capacitors can be well balanced. This method does not requiring sorting voltages from highest to lowest, and just identifies the MIN and MAX capacitor voltage&#x0027;s index which makes it suitable for a modular multilevel converter with a large number of submodules in one arm. Compared to carrier phase-shifted PWM (CPSPWM), this method is more easily to be realized in field-programmable gate array and has much stronger dynamic regulation ability, and is conducive to the control of circulating current. Its feasibility and validity have been verified by simulations and experiments.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6428710]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5063</startPage>
			<endPage>5073</endPage>
			<fileSize>1580</fileSize>
			<authors><![CDATA[Mei, J.;Xiao, B.;Shen, K.;Tolbert, L.M.;Zheng, J.Y.;]]></authors>
		</item>
		<item>
			<title><![CDATA[An Optimal Control Method for Photovoltaic Grid-Tied-Interleaved Flyback Microinverters to Achieve High Efficiency in Wide Load Range]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6457461]]></link>
			<description><![CDATA[Boundary conduction mode (BCM) and discontinuous conduction mode (DCM) control strategies are widely used for the flyback microinverter. The BCM and DCM control strategies are investigated for the interleaved flyback microinverter concentrating on the loss analysis under different load conditions. These two control strategies have different impact on the loss distribution and thus the efficiency of the flyback microinverter. For the interleaved flyback microinverter, the dominant losses with heavy load include the conduction loss of the power MOSFETs and diodes, and the loss of the transformer; while the dominant losses with light load include the gate driving loss, the turn-off loss of the power MOSFETs and the transformer core loss. Based on the loss analysis, a new hybrid control strategy combing the two-phase DCM and one-phase DCM control is proposed to improve the efficiency in wide load range by reducing the dominant losses depending on the load current. The optimal design method based on the boundary condition of the hybrid control is also presented. The experimental results verify the benefits of the proposed control.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6457461]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5074</startPage>
			<endPage>5087</endPage>
			<fileSize>1742</fileSize>
			<authors><![CDATA[Zhang, Z.;He, X.-F.;Liu, Y.-F.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Theoretical and Experimental Analysis of an MPP Detection Algorithm Employing a Single-Voltage Sensor Only and a Noisy Signal]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6457460]]></link>
			<description><![CDATA[In this paper, a maximum power point (MPP) detection algorithm for photovoltaic (PV) systems is introduced, which uses the experimental information obtained from a single-voltage sensor, measured on a capacitor load, either linked at the output of a solar cell (SC), a PV module, or a PV string. The voltage signal is naturally affected by the noise which has a relevant effect on the process necessary for MPP determination, such as voltage first- and second-order derivatives. The aim of this study is to demonstrate the technical feasibility of a maximum power point tracker (MPPT) based on the present MPP detection algorithm employing a single-voltage sensor acquiring a signal affected by the significant noise. Theoretical evaluation, numerical simulations, and experimental measurements are carried out. Excellent agreement between the theoretical and experimental behavior is observed. Conditions for correct MPP detection are shown and good performances are obtained.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6457460]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5088</startPage>
			<endPage>5097</endPage>
			<fileSize>996</fileSize>
			<authors><![CDATA[Dallago, E.;Finarelli, D.G.;Gianazza, U.P.;Barnabei, A.L.;Liberale, A.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Integration and Operation of a Single-Phase Bidirectional Inverter With Two Buck/Boost MPPTs for DC-Distribution Applications]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6471243]]></link>
			<description><![CDATA[This study is focused on integration and operation of a single-phase bidirectional inverter with two buck/boost maximum power point trackers (MPPTs) for dc-distribution applications. In a dc-distribution system, a bidirectional inverter is required to control the power flow between dc bus and ac grid, and to regulate the dc bus to a certain range of voltages. A droop regulation mechanism according to the inverter inductor current levels to reduce capacitor size, balance power flow, and accommodate load variation is proposed. Since the photovoltaic (PV) array voltage can vary from 0 to 600&#x00A0;V, especially with thin-film PV panels, the MPPT topology is formed with buck and boost converters to operate at the dc-bus voltage around 380&#x00A0;V, reducing the voltage stress of its followed inverter. Additionally, the controller can online check the input configuration of the two MPPTs, equally distribute the PV-array output current to the two MPPTs in parallel operation, and switch control laws to smooth out mode transition. A comparison between the conventional boost MPPT and the proposed buck/boost MPPT integrated with a PV inverter is also presented. Experimental results obtained from a 5-kW system have verified the discussion and feasibility.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6471243]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5098</startPage>
			<endPage>5106</endPage>
			<fileSize>1037</fileSize>
			<authors><![CDATA[Wu, T.-F.;Kuo, C.-L.;Sun, K.-H.;Chen, Y.-K.;Chang, Y.-R.;Lee, Y.-D.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Dynamic Stability of a Microgrid With an Active Load]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6415284]]></link>
			<description><![CDATA[Rectifiers and voltage regulators acting as constant power loads form an important part of a microgrid&#x2019;s total load. In simplified form, they present a negative incremental resistance and beyond that, they have control loop dynamics in a similar frequency range to the inverters that may supply a microgrid. Either of these features may lead to a degradation of small-signal damping. It is known that droop control constants need to be chosen with regard to damping, even with simple impedance loads. Actively controlled rectifiers have been modeled in nonlinear state-space form, linearized around an operating point, and joined to network and inverter models. Participation analysis of the eigenvalues of the combined system identified that the low-frequency modes are associated with the voltage controller of the active rectifier and the droop controllers of the inverters. The analysis also reveals that when the active load dc voltage controller is designed with large gains, the voltage controller of the inverter becomes unstable. This dependence has been verified by observing the response of an experimental microgrid to step changes in power demand. Achieving a well-damped response with a conservative stability margin does not compromise normal active rectifier design, but notice should be taken of the inverter&#x2013;rectifier interaction identified.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6415284]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5107</startPage>
			<endPage>5119</endPage>
			<fileSize>9209</fileSize>
			<authors><![CDATA[Bottrell, N.;Prodanovic, M.;Green, T.C.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Variable Delay Time Method in the Phase-Shifted Full-Bridge Converter for Reduced Power Consumption Under Light Load Conditions]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6403557]]></link>
			<description><![CDATA[This paper proposes a new control method in the phase-shifted full-bridge converter for the server power supply, which is variable delay time of lagging-leg switches under the light load conditions. By widening the delay time, the switching occurs at the lower drain&#x2013;source voltage and then switching loss can be reduced under the light load conditions. The voltage stress of synchronous rectifier switches is also reduced. Without additional power devices and side effects at heavy load condition, the higher efficiency under the light load conditions can be obtained. The analysis and experimental results are presented in this paper to confirm the validity of this study.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6403557]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5120</startPage>
			<endPage>5127</endPage>
			<fileSize>691</fileSize>
			<authors><![CDATA[Kim, D.-Y.;Kim, C.-E.;Moon, G.-W.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Secondary-Side Phase-Shift-Controlled ZVS DC/DC Converter With Wide Voltage Gain for High Input Voltage Applications]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6449326]]></link>
			<description><![CDATA[In this paper, a soft-switching dc/dc converter with secondary-side phase-shift control strategy is proposed to improve the conversion efficiency and minimize the primary switch voltage stress in the high input voltage applications. Zero-voltage-switching performance is achieved for both the primary- and secondary-side power devices in a wide load range to reduce the switching losses due to the secondary-side phase-shift control scheme. Furthermore, compared with the conventional phase-shift control mechanism, the circulating current at the freewheeling stage is effectively suppressed as well to minimize the conduction losses. Moreover, the voltage stress of the primary switches is only half of the input voltage by employing the improved three-level structure, which makes the low-voltage rated power devices available to improve the circuit performance. In addition, the converter can work in the buck, balance, and boost modes to achieve a relatively wide input voltage range, which is an expected advantage for the communication power system to minimize the electrolytic capacitors with an acceptable hold-up time. The operation principle is analyzed and experimental results of a 1-kW 100-kHz prototype are provided to verify the effectiveness and the advantages of the proposed converter.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6449326]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5128</startPage>
			<endPage>5139</endPage>
			<fileSize>1237</fileSize>
			<authors><![CDATA[Li, W.;Zong, S.;Liu, F.;Yang, H.;He, X.;Wu, B.;]]></authors>
		</item>
		<item>
			<title><![CDATA[An Isolated Output-Feedback Scheme With Minimized Standby Power for SMPS]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6410436]]></link>
			<description><![CDATA[A feedback network for isolated switch-mode power supplies that automatically reduces the currents flowing through the optocoupler to nearly zero under the no-load condition is presented. This feedback network uses a proposed reverse-type shunt regulator to generate an error signal for optical coupling, and a modified PWM controller is adopted to receive the feedback signal. In comparison to the conventional topology, this proposed one exhibits much lower standby power loss. Besides, light-load efficiency can be improved as well. For implementing the proposed scheme, the PWM controller and the reverse-type shunt regulator are designed and fabricated in VIS 0.5- <formula formulatype="inline"><tex Notation="TeX">$mu$</tex></formula>m 5-V/40-V high-voltage CMOS technology. Experiments reveal that a 12-V/18-W flyback converter prototype which adopts the proposed feedback technique will save a power of at least 27 mW under the no-load condition and improve the system efficiency by 2.2<formula formulatype="inline"><tex Notation="TeX"> $%$</tex></formula> under the 10<formula formulatype="inline"><tex Notation="TeX">$%$</tex></formula>-load (1.8-W output) condition.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6410436]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5140</startPage>
			<endPage>5146</endPage>
			<fileSize>1023</fileSize>
			<authors><![CDATA[Chang, C-.J.;Chen, C-.L.;]]></authors>
		</item>
		<item>
			<title><![CDATA[A Unified Analytical Modeling of the Interleaved Pulse Width Modulation (PWM) DC&#x2013;DC Converter and Its Applications]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6457463]]></link>
			<description><![CDATA[This paper proposes a general methodology to analyze the interleaved pulse width modulation (PWM) dc&#x2013;dc converter. A unified and simple model is constructed and the complete electrical behaviors of the interleaved PWM dc&#x2013;dc converter could be predicted. Features of the interleaved PWM dc&#x2013;dc converter are investigated based on this model. Insightful conclusions are derived and can be used to guide designs. This model could serve as a solid foundation for further research, and it is valid to all the common interleaved PWM dc&#x2013;dc topologies. As an example of its applications, the input current of the interleaved boost converter is investigated in detail. Simulation and experimental results have successfully validated against theoretical analysis.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6457463]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5147</startPage>
			<endPage>5158</endPage>
			<fileSize>1430</fileSize>
			<authors><![CDATA[Zhang, S.;Yu, X.;]]></authors>
		</item>
		<item>
			<title><![CDATA[92&#x0025; High Efficiency and Low Current Mismatch Interleaving Power Factor Correction Controller With Variable Sampling Slope and Automatic Loading Detection Techniques]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6412805]]></link>
			<description><![CDATA[This paper proposes the dual nondeadtime variable sampling slope technique to carry out precise phase sensing and suppress phase error in interleaving power factor correction (PFC) controller over a whole ac switching cycle for low current mismatch. Furthermore, the proposed automatic loading detection (ALD) technique can keep efficiency higher than 92&#x0025; over a wide load range due to accurately controlling the ON/OFF of dual phases. The test circuit fabricated in the TSMC 0.5-&#x03BC;m 800-V UHV process shows that the highly integrated interleaving PFC can deliver a high power of 180&#x00A0;W and a high efficiency of 95&#x0025; at an output power of 180&#x00A0;W.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6412805]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5159</startPage>
			<endPage>5173</endPage>
			<fileSize>2114</fileSize>
			<authors><![CDATA[Su, Y.-P.;Chen, C.-Y.;Ni, C.-L.;Kang, Y.-C.;Chen, Y.-T.;Tsai, J.-C.;Chen, K.-H.;Wang, S.-M.;Liang, C.-C.;Ho, C.-A.;Yu, T.-H.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Low-Noise Switched-Capacitor Power Converter With Adaptive On-Chip Surge Suppression and Preemptive Timing Control]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6415287]]></link>
			<description><![CDATA[An integrated switched-capacitor (SC) power converter is presented in this paper, focusing on input current surge and switching noise suppression. By incorporating an adaptive on-chip surge suppression feedback loop, di/dt switching noise is significantly suppressed, and the start-up inrush current surge can also be greatly reduced. Furthermore, a preemptive timing control scheme is proposed to provide clock signals for each power switch with precisely controlled switching sequence and phase delays, contributing to further switching noise reduction. The proposed converter was fabricated with the AMIS 0.5-&#x03BC;m CMOS process. As the input varying from 2.7 to 4.2&#x00A0;V, the output voltage is regulated at 5&#x00A0;V, with a maximum load current of 25&#x00A0;mA. Compared to a conventional interleaved SC power converter, the proposed design demonstrates 74.7&#x0025; and 80.9&#x0025; reductions on the start-up inrush current surge and steady-state input current perturbation, respectively, and a 60.2&#x0025; output switching noise reduction. The peak efficiency of 90.2&#x0025; is measured at 2.7-V input and 100-mW load.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6415287]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5174</startPage>
			<endPage>5182</endPage>
			<fileSize>1037</fileSize>
			<authors><![CDATA[Zheng, C.;Chowdhury, I.;Ma, D.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Stacked Switched Capacitor Energy Buffer Architecture]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6457459]]></link>
			<description><![CDATA[Electrolytic capacitors are often used for energy buffering applications, including buffering between single-phase ac and dc. While these capacitors have high energy density compared to film and ceramic capacitors, their life is limited. This paper presents a stacked switched capacitor (SSC) energy buffer architecture and some of its topological embodiments, which when used with longer life film capacitors overcome this limitation while achieving effective energy densities comparable to electrolytic capacitors. The architectural approach is introduced along with design and control techniques. A prototype SSC energy buffer using film capacitors, designed for a 320&#x00A0;V dc bus and able to support a 135&#x00A0;W load, has been built and tested with a power factor correction circuit. It is shown that the SSC energy buffer can successfully replace limited-life electrolytic capacitors with much longer life film capacitors, while maintaining volume and efficiency at a comparable level.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6457459]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5183</startPage>
			<endPage>5195</endPage>
			<fileSize>1537</fileSize>
			<authors><![CDATA[Chen, M.;Afridi, K.K.;Perreault, D.J.;]]></authors>
		</item>
		<item>
			<title><![CDATA[A Family of Single-Stage Switched-Capacitor&#x2013;Inductor PWM Converters]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6461420]]></link>
			<description><![CDATA[A family of single-stage-switched-capacitor&#x2013;inductor converters with different voltage conversion features and similar structures is presented in this paper. Unlike conventional switched-capacitor/switched-inductor converters that are produced by cascade operation, all of the proposed converters are operated in single-stage mode. Though each of the proposed converters employs two energy transfer components, i.e., one switched capacitor and one inductor, energy flowing though the two components both directly come from the input power sources and then is directly released to output terminal. This design can meet the high efficiency requirement and simple structure. A small resonant inductor is also used in these converters to limit the current peak caused by switched capacitors and to improve efficiency. The detailed analysis of circuit operation and design consideration is given. Simulation and experimental results are also provided to verify the performance of the new family of converters.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6461420]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5196</startPage>
			<endPage>5205</endPage>
			<fileSize>1358</fileSize>
			<authors><![CDATA[Ye, Y.;Cheng, K.W.E.;]]></authors>
		</item>
		<item>
			<title><![CDATA[A Bridgeless Boost Rectifier for Low-Voltage Energy Harvesting Applications]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6421002]]></link>
			<description><![CDATA[In this paper, a single-stage ac&#x2013;dc power electronic converter is proposed to efficiently manage the energy harvested from electromagnetic microscale and mesoscale generators with low-voltage outputs. The proposed topology combines a boost converter and a buck-boost converter to condition the positive and negative half portions of the input ac voltage, respectively. Only one inductor and capacitor are used in both circuitries to reduce the size of the converter. A 2&#x00A0;cm&#x00A0;&#x00D7;&#x00A0;2&#x00A0;cm, 3.34-g prototype has been designed and tested at 50-kHz switching frequency, which demonstrate 71&#x0025; efficiency at 54.5 mW. The input ac voltage with 0.4-V amplitude is rectified and stepped up to 3.3-V dc. Detailed design guidelines are provided with the purpose of minimizing the size, weight, and power losses. The theoretical analyses are validated by the experiment results.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6421002]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5206</startPage>
			<endPage>5214</endPage>
			<fileSize>950</fileSize>
			<authors><![CDATA[Wang, H.;Tang, Y.;Khaligh, A.;]]></authors>
		</item>
		<item>
			<title><![CDATA[A Class-<formula formulatype="inline"> <img src="/images/tex/607.gif" alt="E"> </formula> RF Power Amplifier With a Flat-Top Transistor-Voltage Waveform]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6418041]]></link>
			<description><![CDATA[This paper shows a new class-<formula formulatype="inline"><tex Notation="TeX">$E$</tex></formula> amplifier topology with the objective to increase the nominal class-<formula formulatype="inline"><tex Notation="TeX">$E$</tex></formula> output power for a given voltage and current stress on the power transistor. To obtain that result, a parallel LC resonator is added to the load network, tuned to the second harmonic of the switching frequency. A class-<formula formulatype="inline"><tex Notation="TeX">$E$</tex></formula> power amplifier is obtained whose transistor-voltage waveform peak value is 81&#x0025; of the peak value of the voltage of a nominal class- <formula formulatype="inline"><tex Notation="TeX">$E$</tex></formula> amplifier using the same dc supply voltage. In this amplifier, the peak voltage across the transistor is 3.0&#x00A0;times the dc supply voltage, instead of the 3.6&#x00A0;times associated with nominal class-<formula formulatype="inline"><tex Notation="TeX">$E$</tex></formula> amplifiers. A normalized design is presented, and the behavior of the circuit is analyzed with simulation showing that the ratio of output power versus transistor peak voltage times peak current is 20.4&#x0025; better than the nominal class <formula formulatype="inline"><tex Notation="TeX">$E$</tex></formula>. The proposed converter and normalized design approach are verified by simulations and measurements done on an experimental prototype.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6418041]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5215</startPage>
			<endPage>5221</endPage>
			<fileSize>1340</fileSize>
			<authors><![CDATA[Mediano, A.;Sokal, N.O.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Analysis and Design of Class-E Power Amplifier With MOSFET Parasitic Linear and Nonlinear Capacitances at Any Duty Ratio]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6470692]]></link>
			<description><![CDATA[This paper presents analytical expressions for the class-E power amplifier with MOSFET linear gate-to-drain and nonlinear drain-to-source parasitic capacitances at any duty ratio. The maximum operating frequency, output power capability, and element values as functions of the duty ratio are obtained. The element values are directly dependent upon the selection of duty ratio and require a careful duty ratio selection to minimize component power losses and to maximize the total efficiency. Two design examples at 25 and 9&#x00A0;W output power at 4-MHz operating frequency along with the PSpice-simulation and experimental waveforms are presented. It is shown from the derived expressions that the slope of the voltage across the MOSFET gate-to-drain parasitic capacitance during the switch-off state as a function of the duty ratio affects the switch-voltage waveform. Therefore, it is possible to achieve the required peak switch voltage and the class-E ZVS/ZVDS conditions simultaneously by adjusting the duty ratio. The theoretical results and PSpice simulations agreed with experimental results quantitatively, which shows the validity of the presented analysis.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6470692]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5222</startPage>
			<endPage>5232</endPage>
			<fileSize>1494</fileSize>
			<authors><![CDATA[Hayati, M.;Lotfi, A.;Kazimierczuk, M.K.;Sekiya, H.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Load Detection Model of Voltage-Fed Inductive Power Transfer System]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6425491]]></link>
			<description><![CDATA[Detecting load parameters in the inductive power transfer (IPT) system is essential to establishing a stable and efficient wireless power supply of good quality for kitchen appliances. This paper presents an effective load detection approach, namely transient load detection model, to detect load conditions by utilizing the energy injection mode and free resonant mode. To realize the proposed model, the differential equation of the primary resonant current under the free resonant mode was used. Besides, real-time sampled data, including the operating frequency in the free resonant mode and peak value of the primary resonant current were collected. Imitating the wireless power supply for kitchen appliances, simulation and experimental results with the full-bridge SS-type voltage-fed IPT system have shown that this transient load detection model is accurate and reliable.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6425491]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5233</startPage>
			<endPage>5243</endPage>
			<fileSize>1528</fileSize>
			<authors><![CDATA[Wang, Z.-H.;Li, Y.-P.;Sun, Y.;Tang, C.-S.;Lv, X.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Avoiding a Voltage Sag Detection Stage for a Single-Phase Multilevel Rectifier by Using Control Theory Considering Physical Limitations of the System]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6408391]]></link>
			<description><![CDATA[The use of control theory in power electronics applications is aimed toward several objectives, which include, obtaining a good dynamic response, stabilizing in an operation point, regulation of state variable, reference tracking, rejecting of disturbances and robustness against parametric variations. It is also possible to eliminate stages that represent computational effort via control theory without loss of the main desirable characteristics. However, it should be considered the physical limitations of the topology given that even with sophisticated controllers they cannot achieve the established objectives if these limitations are exceeded. This paper aims at highlighting the importance of physical limitations of a single-phase multilevel rectifier (SPMR) using a nonlinear controller, an aspect not considered in previous works published by the authors. Thus, the design here presented is based on input&#x2013;output linearization via feedback combined with a generalized PI controller. These controllers are used because they allow avoiding a voltage sag detection stage without changing the main characteristics of the topology. The procedure to reproduce these results is shown and the feasibility of the method is demonstrated by simulation and experimental results in a 1 kVA SPMR prototype.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6408391]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5244</startPage>
			<endPage>5251</endPage>
			<fileSize>1224</fileSize>
			<authors><![CDATA[Visairo, N.;Nunez, C.;Lira, J.;Lazaro, I.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Control Scheme With Voltage Support Capability for Distributed Generation Inverters Under Voltage Sags]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6459042]]></link>
			<description><![CDATA[Voltage sags are one of the main problems in transmission and distribution grids with high penetration of distributed generation. This paper proposes a voltage support control scheme for grid-connected power sources under voltage sags. The control is based on the injection of reactive current with a variable ratio between positive and negative sequences. The controller determines, also, the amount of reactive power needed to restore the dropped voltage magnitudes to new reference values confined within the continuous operation limits required in grid codes. These reference values are chosen in order to guarantee low current injection when fulfilling the voltage support objective. Selected experimental results are reported in order to validate the effectiveness of the proposed control.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6459042]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5252</startPage>
			<endPage>5262</endPage>
			<fileSize>1287</fileSize>
			<authors><![CDATA[Miret, J.;Camacho, A.;Castilla, M.;de Vicuna, L.G.;Matas, J.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Predictive Fast DSP-Based Current Controller for a 12-Pulse Hybrid-Mode Thyristor Rectifier]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6423942]]></link>
			<description><![CDATA[This paper proposes a novel 12-pulse hybrid-mode thyristor rectifier (HMTR) that can operate in either parallel mode or series mode with the help of a switch. No matter in which mode it operates, the proposed 12-pulse HMTR keeps the same pulses in the load current. It is designed to operate in parallel mode when low output voltage is required and in series mode when high output voltage is required. This way, the firing angle of the thyristor is reduced and thereby the total harmonic distortion (THD) in the input current is improved. The predictive current control strategy is also proposed to achieve the hybrid-mode operation. Fast current response is achieved both in parallel and series modes as well as in transitions between parallel and series modes. The concept of the proposed predictive current control scheme is quite simple and understandable, and easy to be implemented by a microprocessor. This paper includes analysis, simulation, experiment, and a comparison of the proposed control method with the conventional PI controller. Results from both simulation and experiment demonstrate the validity of the proposed 12-pulse HMTR and the effectiveness of the predictive current control algorithm.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6423942]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5263</startPage>
			<endPage>5271</endPage>
			<fileSize>1435</fileSize>
			<authors><![CDATA[Damin, Z.;Shitao, W.;Fengwu, Z.;Lujun, W.;Zhengyu, L.;]]></authors>
		</item>
		<item>
			<title><![CDATA[An Islanding Microgrid Power Sharing Approach Using Enhanced Virtual Impedance Control Scheme]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6423938]]></link>
			<description><![CDATA[In order to address the load sharing problem in islanding microgrids, this paper proposes an enhanced distributed generation (DG) unit virtual impedance control approach. The proposed method can realize accurate regulation of DG unit equivalent impedance at both fundamental and selected harmonic frequencies. In contrast to conventional virtual impedance control methods, where only a line current feed-forward term is added to the DG voltage reference, the proposed virtual impedance at fundamental and harmonic frequencies is regulated using DG line current and point of common coupling (PCC) voltage feed-forward terms, respectively. With this modification, the impacts of mismatched physical feeder impedances are compensated. Thus, better reactive and harmonic power sharing can be realized. Additionally, this paper also demonstrates that PCC harmonic voltages can be mitigated by reducing the magnitude of DG unit equivalent harmonic impedance. Finally, in order to alleviate the computing load at DG unit local controller, this paper further exploits the band-pass capability of conventionally resonant controllers. With the implementation of proposed resonant controller, accurate power sharing and PCC harmonic voltage compensation are achieved without using any fundamental and harmonic components extractions. Experimental results from a scaled single-phase microgrid prototype are provided to validate the feasibility of the proposed virtual impedance control approach.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6423938]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5272</startPage>
			<endPage>5282</endPage>
			<fileSize>1313</fileSize>
			<authors><![CDATA[He, J.;Li, Y.W.;Guerrero, J.M.;Blaabjerg, F.;Vasquez, J.C.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Control Strategy for Input-Series-Output-Series High-Frequency AC-Link Inverters]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6466392]]></link>
			<description><![CDATA[This paper presents a control strategy for input-series-output-series (ISOS) modular inverters. Each module is a bidirectional high-frequency ac-link (HFACL) inverter composed of an HF inverter, an HF transformer followed by a cycloconverter. The relationship between input voltage sharing (IVS) and output voltage sharing (OVS) is revealed with a general load based on bidirectional ISOS inverter systems. To achieve IVS and OVS, a stable power sharing control strategy eliminating mandatory IVS loops is proposed. For individual modules, the common output voltage regulation loop output multiplies its magnitude compensator loop output to work as its pulse width modulation signal. The loop gain design is also presented. With the proposed control strategy, excellent IVS and OVS can be obtained not only during steady state but also during transients. The effectiveness of the proposed control strategy is verified by simulation and experimental results of a 2420-VA ISOS two HFACL inverters.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6466392]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5283</startPage>
			<endPage>5292</endPage>
			<fileSize>2040</fileSize>
			<authors><![CDATA[Sha, D.;Xu, G.;Liao, X.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Self-Sustained Oscillating Control Technique for Current-Driven Full-Bridge DC/DC Converter]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6423941]]></link>
			<description><![CDATA[This paper presents a novel control approach for a current-driven full-bridge dc/dc converter, which is able to significantly improve the converter performance over a very wide range of operating conditions. The proposed control approach is based on the self-sustained oscillating control (SSOC) scheme, in order to adaptively change the phase shift and the switching frequency of the converter for different operating points. In this control technique, the timing signal is produced based on the transformer primary current, which is a feedback to the control system to determine the switching instants of the power MOSFETs. Therefore, the control system automatically tunes the control variables for different operating conditions. The comprehensive mathematical analysis of the proposed SSOC scheme is presented in detail. The mathematical analysis is based on the geometric viewpoint of the control system, which provides a very good insight into designing the control system. Experimental results provided from a 3 kW prototype confirm the feasibility of the proposed scheme and prove the superiority of the performance compared to the conventional phase-shift control approach.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6423941]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5293</startPage>
			<endPage>5310</endPage>
			<fileSize>2107</fileSize>
			<authors><![CDATA[Pahlevaninezhad, M.;Eren, S.;Jain, P.K.;Bakhshai, A.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Effect of Control Method on Impedance-Based Interactions in a Buck Converter]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6461965]]></link>
			<description><![CDATA[All the interconnected regulated systems are prone to impedance-based interactions making them sensitive to instability and transient-performance degradation. The applied control method affects significantly the characteristics of the converter in terms of sensitivity to different impedance interactions. This paper provides for the first time the whole set of impedance-type internal parameters and the formulas according to which the interaction sensitivity can be fully explained and analyzed. The formulation given in this paper can be utilized equally either based on measured frequency responses or on predicted analytic transfer functions. Usually, the distributed dc&#x2013;dc systems are constructed by using ready-made power modules without having thorough knowledge on the actual power-stage and control-system designs. As a consequence, the interaction characterization has to be based on the frequency responses measureable via the input and output terminals. A buck converter with four different control methods is experimentally characterized in frequency domain to demonstrate the effect of control method on the interaction sensitivity. The presented analytical models are used to explain the phenomena behind the changes in the interaction sensitivity.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6461965]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5311</startPage>
			<endPage>5322</endPage>
			<fileSize>580</fileSize>
			<authors><![CDATA[Vesti, S.;Suntio, T.;Oliver, J.A.;Prieto, R.;Cobos, J.A.;]]></authors>
		</item>
		<item>
			<title><![CDATA[State-Plane Analysis of Regenerative Snubber for Flyback Converters]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6423935]]></link>
			<description><![CDATA[The flyback converter is a popular topology for implementing low power and multiple output power supplies. However, the high leakage inductance of the flyback transformer causes high voltage spikes that can damage the main transistor when the switch is turned OFF. Therefore, a turn-off snubber is needed to limit the peak voltage stress. This paper presents the analysis of an energy regenerative snubber using the graphical state-plane technique. The undertaken approach yields a clear-cut design procedure for minimum switch voltage stress. Experimental evaluation of the energy regenerative snubber in comparison with other common snubbers shows that under the same voltage stress the efficiency of energy regenerative snubber has 8&#x0025; improvement on average over an RCD snubber and 2&#x0025; improvement over the nondissipative LC snubber.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6423935]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5323</startPage>
			<endPage>5332</endPage>
			<fileSize>646</fileSize>
			<authors><![CDATA[Abramovitz, A.;Liao, C.-S.;Smedley, K.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Simplified Discrete-Time Modeling for Convenient Stability Prediction and Digital Control Design]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6459043]]></link>
			<description><![CDATA[This paper presents a simplified discrete-time modeling method for digital-controlled switching power converters. Reserving the utility of fast-scale dynamics analysis, the method introduces state-space average technique into the conventional discrete-time modeling scheme. Compared to the conventional discrete-time models, the simplified models have almost the same reliability and accuracy in stability prediction in most practical applications. In addition, they also lend themselves more convenient to digital control design than do the exact discrete-time models due to their obvious simplicity. Taking a current-mode-controlled boost dc&#x2013;dc converter and a digital-controlled single-phase full-bridge dc&#x2013;ac inverter as practical examples, the simplified modeling approach is validated by simulations and experiments.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6459043]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5333</startPage>
			<endPage>5342</endPage>
			<fileSize>1696</fileSize>
			<authors><![CDATA[Wu, X.;Xiao, G.;Lei, B.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Model Predictive Direct Power Control of a PWM Rectifier With Duty Cycle Optimization]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6423943]]></link>
			<description><![CDATA[This paper proposes an improved model predictive direct power control (MPDPC) for a pulse width modulation (PWM) rectifier by using a duty cycle control. The conventional MPDPC achieves good steady-state performance and quick dynamic response by selecting the best voltage vector, which minimizes the errors between the reference power and the real power. However, due to the limited number of voltage vectors in a two-level converter, the sampling frequency has to be high to achieve satisfactory performance. This paper introduces the concept of a duty cycle control in the MPDPC by allocating a fraction of control period for a nonzero voltage vector and the rest time for a zero vector. The nonzero vector is selected by evaluating the effects of each nonzero vector and its duration is obtained based on the principle of power errors minimization. Simulation and experimental results prove that, compared to the conventional MPDPC, the proposed MPDPC with duty cycle achieves further steady-state performance improvement without affecting the dynamic response at a small cost of control complexity increase.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6423943]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5343</startPage>
			<endPage>5351</endPage>
			<fileSize>1234</fileSize>
			<authors><![CDATA[Zhang, Y.;Xie, W.;Li, Z.;Zhang, Y.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Stability Analysis and Design Procedure of Multiloop Linear LDO Regulators via State Matrix Decomposition]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6415285]]></link>
			<description><![CDATA[This paper presents the application of the state space approach to analyze stability and robustness of multiloop linear low dropout (LDO) regulators. Because of the increasing complexity of the LDO architecture, the stability study consisting of an open-loop ac analysis is more and more difficult to apply. In this paper, we demonstrate how a state matrix decomposition of a system allows the stability analysis in closed loop to be performed where the open-loop ac analysis failed. Based on this technique, a methodology of design, a time response criterion, and a Monte Carlo analysis are proposed. The efficiency of this approach is illustrated comparing the classical open-loop ac study with the state matrix decomposition analysis of a complex innovative architecture LDO. The results are verified experimentally.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6415285]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5352</startPage>
			<endPage>5363</endPage>
			<fileSize>1323</fileSize>
			<authors><![CDATA[Coulot, T.;Lauga-Larroze, E.;Fournier, J.-M.;Alamir, M.;Hasbani, F.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Common-Mode Filter Design for PWM Rectifier-Based Motor Drives]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6408361]]></link>
			<description><![CDATA[A common-mode (CM) filter based on the LCL filter topology is proposed in this paper, which provides a parallel path for ground currents and which also restricts the magnitude of the EMI noise injected into the grid. The CM filter makes use of the components of a line to line LCL filter, which is modified to address the CM voltage with minimal additional components. This leads to a compact filtering solution. The CM voltage of an adjustable speed drive using a PWM rectifier is analyzed for this purpose. The filter design is based on the CM equivalent circuit of the drive system. The filter addresses the adverse effects of the PWM rectifier in an adjustable speed drive. Guidelines are provided on the selection of the filter components. Different variants of the filter topology are evaluated to establish the effectiveness of the proposed circuit. Experimental results based on EMI measurement on the grid side and the CM current measurement on the motor side are presented. These results validate the effectiveness of the filter.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6408361]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5364</startPage>
			<endPage>5371</endPage>
			<fileSize>1384</fileSize>
			<authors><![CDATA[Hedayati, M.H.;Acharya, A.B.;John, V.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Analytical Modeling of Sideband Current Harmonic Components in Induction Machine Drive With Voltage Source Inverter by an SVM Technique]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6415286]]></link>
			<description><![CDATA[The sideband current harmonic components are practically inevitable in induction motor drive systems with voltage source inverter and pulse width modulation technique. However, those particular harmonic components would increase the losses, torque ripple, and electromagnetic noise so as to deteriorate the overall performance of the electric machine. In this paper, the main sideband current harmonic components in induction machines driven by voltage source inverter with space vector pulse width modulation technique are analytically derived and expressed in both stator and synchronous dq reference frames, which could be employed as a rapid analytical tool to study the corresponding harmonic losses, torque pulsations, and electromagnetic noises. The validity of the analytical models has been confirmed by the experimental results. Finally, both the load characteristics and impact factors on the sideband current harmonics in induction machine drives are comprehensively investigated and discussed based on the analytical models.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6415286]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5372</startPage>
			<endPage>5379</endPage>
			<fileSize>771</fileSize>
			<authors><![CDATA[Liang, W.;Wang, J.;Fang, W.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Precise Braking Torque Control for Attitude Control Flywheel With Small Inductance Brushless DC Motor]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6451293]]></link>
			<description><![CDATA[In this paper, a newly designed braking torque control scheme with improved toque estimation and control characteristics in a small inductance brushless DC motor is presented. The motor torque is estimated according to the back electromotive force (EMF) shape function that is fitted by neural network and corrected by temperature. Upon this, a hybrid braking torque control structure that combines dynamic braking and plug braking is proposed for the smooth and continuous braking torque. These two braking modes operate, respectively, in the relatively high- and low-speed ranges. During dynamic braking, a predictive torque control method is proposed to suppress the torque fluctuation that is induced by the supplying voltage namely back EMF descent. During plug braking, an effective torque ripple reduction method is designed to weaken the large torque ripple which is caused by high winding voltage, low winding impedance, and three-phase inverter modulation. In addition, different pulse width modulation patterns and the most suitable operating conditions for each braking mode have been studied. Finally, experimental results are presented to demonstrate the validity and effectiveness of the proposed braking torque control scheme.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6451293]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5380</startPage>
			<endPage>5390</endPage>
			<fileSize>1211</fileSize>
			<authors><![CDATA[Zhou, X.;Fang, J.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Analysis of Supercapacitor Energy Loss for Power Management in Environmentally Powered Wireless Sensor Nodes]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6408393]]></link>
			<description><![CDATA[This paper analyzes supercapacitor energy loss and investigates its impact on power management in environmentally powered wireless sensor nodes that use supercapacitor-based energy storage systems. While supercapacitor self-discharge is usually taken into account for system design and power management in wireless sensor nodes, supercapacitor charge redistribution and the associated energy loss have not been considered. In an environmentally powered wireless sensor node, supercapacitor charge redistribution may have more significant impact on power management than self-discharge. This paper analyzes supercapacitor energy loss during charge redistribution based on the variable leakage resistance (VLR) model. It is concluded that supercapacitor energy loss is dependent on charge redistribution time and supercapacitor initial state, which is defined as the initial voltages across the capacitors in the VLR model. The impact of supercapacitor energy loss on power management is studied by considering the task scheduling problem. A set of simulation cases that covers various supercapacitor initial state and energy harvesting capability is designed to investigate the impact of supercapacitor energy loss on task scheduling policy. It is demonstrated that greedy or lazy scheduling policy is preferred depending on supercapacitor initial state and energy harvesting capability in terms of two performance evaluation metrics.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6408393]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5391</startPage>
			<endPage>5403</endPage>
			<fileSize>1662</fileSize>
			<authors><![CDATA[Yang, H.;Zhang, Y.;]]></authors>
		</item>
		<item>
			<title><![CDATA[High-Bandwidth High-Temperature (250 &#x00B0;C/500 &#x00B0;F) Isolated DC and AC Current Measurement: Bidirectionally Saturated Current Transformer]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6464605]]></link>
			<description><![CDATA[In an increasing number of application areas and industry sectors, such as the automotive, aerospace, military or oil and gas industry, a trend towards higher ambient temperature rating from 85 <formula formulatype="inline"><tex Notation="TeX">$^circ$</tex></formula>C upwards for electrical machines and power electronic converters can be observed. To reduce the impact of high ambient temperatures on the power density, the interest in power electronic converters with SiC power semiconductors operated up to a junction temperature of 250 <formula formulatype="inline"><tex Notation="TeX">$^circ$</tex></formula>C rises. The control of power electronic converters typically requires a precise, fast, and robust current measurement. However, analyzing current measurement concepts from the literature reveals that there is a lack of measurement systems, that are galvanically isolated and able to measure dc and higher frequency ac currents fast at high ambient temperatures of 250 <formula formulatype="inline"> <tex Notation="TeX">$^circ$</tex></formula>C. In this paper, a current measurement concept of a bidirectionally saturated current transformer is presented, that is able to measure dc and sinusoidal ac up to 1&#x00A0;kHz and 50 &#x00A0;A at an ambient temperature of 250 <formula formulatype="inline"><tex Notation="TeX">$^circ$</tex></formula>C with an relative error of 2.6&#x0025; and less than 0.5&#x0025; error after initial calibration. Furthermore, a prototype is designed, built, and used for the experimental verification of the concept.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6464605]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5404</startPage>
			<endPage>5413</endPage>
			<fileSize>1067</fileSize>
			<authors><![CDATA[Wrzecionko, B.;Steinmann, L.;Kolar, J.W.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Multiprobe Measurement Method for Voltage-Dependent Capacitances of Power Semiconductor Devices in High Voltage]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6410437]]></link>
			<description><![CDATA[The characterization of voltage-dependent capacitances of power semiconductor devices [diode, MOSFET, insulated gate bipolar transistor (IGBT), etc.] is very important for modeling their dynamic performances. A measurement method using two current probes has been developed to characterize interelectrode capacitances of power devices while isolating the measurement devices from the high-voltage dc bias power source. <formula formulatype="inline"><tex Notation="TeX">$C_{{rm iss}}$</tex></formula> and <formula formulatype="inline"><tex Notation="TeX">$C_{{rm oss}}$</tex></formula> are shown to be accurately measured while <formula formulatype="inline"><tex Notation="TeX">$C_{{rm rss}}$ </tex></formula> is not convincing enough. Then an additional current probe is added to improve the method. <formula formulatype="inline"><tex Notation="TeX">$C_{{rm rss}}$</tex></formula> is shown to be well characterized by this three-current-probe method. This method has been validated using various technologies of semiconductor devices including silicon MOSFET and silicon carbide JFET. The interelectrode capacitances of power devices can be safely and accurately measured with this multiprobe method even in high voltage.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6410437]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5414</startPage>
			<endPage>5422</endPage>
			<fileSize>814</fileSize>
			<authors><![CDATA[Li, K.;Videt, A.;Idir, N.;]]></authors>
		</item>
		<item>
			<title><![CDATA[A Resonant Gate-Drive Circuit With Optically Isolated Control Signal and Power Supply for Fast-Switching and High-Voltage Power Semiconductor Devices]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6461964]]></link>
			<description><![CDATA[This paper deals with a resonant gate-drive circuit for fast-switching and high-voltage power semiconductor devices, which is equipped with optical fibers for both gate control signal and dc power supply. A resonant inductor connected with the gate terminal makes it possible to charge or discharge the gate-to-source voltage by using the parallel resonance between the inductor and the input capacitance of the device. The optical fibers can be used to deliver the driving power to the gate-drive circuit, because the circuit theoretically causes no power consumption for driving the power device. Moreover, the proposed circuit makes it possible to suppress fluctuations in the gate voltage caused by a rapid change in the drain-to-source voltage. Experimental results are shown to verify the viability of the proposed circuit.]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6461964]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5423</startPage>
			<endPage>5430</endPage>
			<fileSize>497</fileSize>
			<authors><![CDATA[Fujita, H.;]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Transactions on Power Electronics information for authors]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514568]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514568]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>5431</startPage>
			<endPage>5432</endPage>
			<fileSize>164</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Power Electronics Society Information]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514584]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514584]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>C3</startPage>
			<endPage>C3</endPage>
			<fileSize>121</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[Blank page]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514660]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Nov.  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6514660]]></guid>
			<volume>28</volume>
			<issue>11</issue>
			<startPage>C4</startPage>
			<endPage>C4</endPage>
			<fileSize>5</fileSize>
			<authors><![CDATA[]]></authors>
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