<![CDATA[ IEEE Transactions on Power Electronics - new TOC ]]>
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TOC Alert for Publication# 63 2017May 25<![CDATA[Table of Contents]]>3210C1C456<![CDATA[IEEE Power Electronics Society]]>3210C2C260<![CDATA[Impedance Analysis of SOGI-FLL-Based Grid Synchronization]]>321074097413523<![CDATA[An Optimized Three-Phase Multilevel Inverter Topology With Separate Level and Phase Sequence Generation Part]]>3210741474182513<![CDATA[An Improved Virtual Space Vector Modulation Scheme for Three-Level Active Neutral-Point-Clamped Inverter]]>3210741974342647<![CDATA[A Review of Hybrid Topologies Combining Line-Commutated and Cascaded Full-Bridge Converters]]>3210743574481109<![CDATA[A Boost PFC Stage Utilized as Half-Bridge Converter for High-Efficiency DC–DC Stage in Power Supply Unit]]>LLC converter is one of the most attractive dc–dc converters for medium power supplies due to its soft switching capability. However, its conversion efficiency is considerably degraded in wide-link-voltage applications because of a small magnetizing inductance and wide switching frequency variation for a high voltage gain. In this paper, a boost power factor correction (PFC) stage, which can also play an important role during the hold-up time, is proposed for a high-efficiency HB LLC converter. In the proposed PFC stage, the boost PFC converter can be effectively utilized as a HB converter by replacing a boost diode and inductor with a synchronous switch and transformer, respectively. After the ac line is lost, the proposed PFC stage can operate as the HB converter and regulate the output voltage instead of the HB LLC converter. Thus, it enables the HB LLC converter to be designed with a large magnetizing inductance and narrow switching frequency variation. As a result, the proposed PFC stage can enhance the overall efficiency of the PSU by improving the efficiency of the HB LLC converter. To confirm the validity of this paper, a prototype with 180–264-Vrms ac line, 250–400-V link voltage, and 48 V/480 W output is tested.]]>3210744974571083<![CDATA[Reduced Active Switch Front-End Multipulse Rectifier With Medium-Frequency Transformer Isolation]]>l-l, 3.15 kW laboratory prototype are presented to validate the performance of the proposed approach.]]>3210745874681272<![CDATA[A Hybrid Active Gate Drive for Switching Loss Reduction and Voltage Balancing of Series-Connected IGBTs]]>3210746974811322<![CDATA[Novel Eliminated Common-Mode Voltage PWM Sequences and an Online Algorithm to Reduce Current Ripple for a Three-Level Inverter]]>n-inverter, is proposed. Harmonic performance and switching loss characteristic of the proposed ZCMV PWM have been compared to those of a conventional space-vector PWM and a three-state ZCMV PWM with reduced current ripple. Comparative analytical results verified by experimentation have shown that the proposed PWM scheme reduces the current harmonic distortion considerably in a high modulation index range of a 3L NPC inverter.]]>3210748274933137<![CDATA[A Closed-Loop Time-Domain Analysis Method for Modular Multilevel Converter]]>3210749475084013<![CDATA[Cascaded Dual-Buck AC–AC Converter With Reduced Number of Inductors]]>3210750975202543<![CDATA[A Modulation Strategy to Operate Multilevel Multiphase Diode-Clamped and Active-Clamped DC–AC Converters at Low Frequency Modulation Indices With DC-Link Capacitor Voltage Balance]]>n-level three-phase case. Subsequently, it is extended to higher number of switching transitions per fundamental cycle and to higher number of phases. Simulation results with three, four, and five levels; three and five phases; and several frequency-modulation-index values are presented to validate the proposed modulation strategy. Experimental results obtained with a four-level three-phase dc–ac converter prototype are also provided. The proposed modulation strategy enables the use of this type of converters in applications where the ac fundamental frequency may be close to the switching frequency, such as in high-power systems and variable-speed motor drives.]]>3210752175332929<![CDATA[Design and Experimental Testing of a Resonant DC–DC Converter for Solid-State Transformers]]>3210753475421928<![CDATA[Improved Dual Boost Inverter With Half Cycle Modulation]]>3210754375521087<![CDATA[Natural Sampling SVM-Based Common-Mode Voltage Reduction in Medium-Voltage Current Source Rectifier]]>LC filter of the converter, thus, introducing resonance as the grid-side damping is small. Recently, a natural sampling SVM (NS-SVM) with superior low-order harmonics performance has been proposed for MV CSR. On this basis, a NS-SVM-based CMV reduction method is proposed for MV CSR in this paper. The proposed scheme achieves both good CMV reduction and superior low-order harmonics performance simultaneously. Additionally, effort to lower computational burden on calculating dwell times is made. Experiments are finally provided.]]>3210755375602946<![CDATA[Closed-Form Solution for Efficient ZVS Modulation of DAB Converters]]>$\text{3.7}\; \text{kW}$ converter prototype which interfaces a $\text{400}\; \text{V}$ battery with the $\text{230}\;\text{V}$, $\text{50}\;\text{Hz}$ utility grid are given to validate the theoretical analysis and practical feasibility of the proposed strategy.]]>3210756175762623<![CDATA[Adaptive Thyristor-Controlled LC-Hybrid Active Power Filter for Reactive Power and Current Harmonics Compensation With Switching Loss Reduction]]>3210757775902884<![CDATA[Single-Stage Three-Phase Current-Source Photovoltaic Grid-Connected Inverter High Voltage Transmission Ratio]]>CL filter, low output current total harmonic distortion, and flexible voltage configuration of the PV cells. This study provides an effective design method for single-stage three-phase inverting with high VTR.]]>3210759176013701<![CDATA[A PV Power Conditioning System Using Nonregenerative Single-Sourced Trinary Asymmetric Multilevel Inverter With Hybrid Control Scheme and Reduced Leakage Current]]>3210760276146590<![CDATA[Single-Phase Inverter With Energy Buffer and DC–DC Conversion Circuits]]>3210761576253190<![CDATA[SOC Estimation of Lithium-Ion Batteries With AEKF and Wavelet Transform Matrix]]>2 battery module with nominal capacity of 200 Ah and rated voltage of 3.6 V. SOC estimation error with the proposed denoising approach is limited within 1%. Compared to the maximum error of 2.5% using an adaptive extended Kalman filter without denoising, an estimation error reduction of 1.5% is achieved.]]>3210762676346146<![CDATA[A Comprehensive Analysis and Control Strategy for Nullifying Negative- and Zero-Sequence Currents in an Unbalanced Three-Phase Power System Using Electric Springs]]>3210763576502525<![CDATA[Active Phase Control for Maximum Power Point Tracking of a Linear Wave Generator]]>3210765176621853<![CDATA[A Novel Self-Power SSHI Circuit for Piezoelectric Energy Harvester]]>3210766376731827<![CDATA[Sequence-Impedance-Based Harmonic Stability Analysis and Controller Parameter Design of Three-Phase Inverter-Based Multibus AC Power Systems]]>3210767476933735<![CDATA[A Switched-Coupling-Capacitor Equalizer for Series-Connected Battery Strings]]>mosfets are controlled by one pair of complementary pulse width modulation signals, and energy can be automatically and directly delivered from any higher voltage cells to any lower voltage ones without the need of cell monitoring circuits, leading to a high balancing efficiency and speed independent of the cell number and the initial cell voltages. Contrary to the conventional equalizers using additional components for the equalization among modules, the proposed equalizer shares a single converter for the equalization among cells and modules, resulting in smaller size and lower cost. A prototype for four lithium battery cells is implemented, and an experimental comparison between the proposed SCCE and the conventional SC equalizer is presented. Experimental results show the proposed topology exhibits a substantially improved balancing performance, and the measured peak efficiency is 92.7%.]]>3210769477064528<![CDATA[A High-Voltage-Gain DC–DC Converter Based on Modified Dickson Charge Pump Voltage Multiplier]]>${V}_{rm{in}}= rm{ 20}$ and ${V}_{rm{out}}= rm{ 400}$ V has been developed to validate the analytical results.]]>3210770777151328<![CDATA[A Soft-Switching Bridgeless AC–DC Power Factor Correction Converter]]>3210771677262121<![CDATA[Performance Evaluation of a Semi-Dual-Bridge Resonant DC/DC Converter With Secondary Phase-Shifted Control]]>3210772777381271<![CDATA[A High Step-up PWM DC-DC Converter With Coupled-Inductor and Resonant Switched-Capacitor]]>3210773977491393<![CDATA[Design of a Highly Efficient (97.7%) and Very Compact (2.2 kW/dm $^3$) Isolated AC–DC Telecom Power Supply Module Based on the Multicell ISOP Converter Approach]]>$text{230},V_text{AC}/text{48}, V_text{DC}$ telecom power supply with $N_{text{cells}}=6$ isolated converter cells in an input-series output-parallel arrangement is presented with measurement results indicating a maximum efficiency of $eta =$ 97.7% and a power density of $rho =$ 2.2 kW/dm^{3} (= 36 W/in^{3}). Furthermore, different paths for future performance improvements of the multicell arrangement are outlined.]]>3210775077692434<![CDATA[Power Stage and Feedback Loop Design for LLC Resonant Converter in High-Switching-Frequency Operation]]>LLC resonant converters. At high-switching-frequency operation, the power stage design must take secondary leakage inductance into account because it can affect the input–output voltage gain. In addition, the feedback loop design should consider the effect of the time delay caused by the performance limitation of a digital controller to improve the small-signal model accuracy of the converter. Using the proposed power stage and feedback control loop design considerations, the LLC resonant converter can achieve high power conversion efficiency and stability enhancement at high switching frequencies. All the proposed methods are experimentally verified using a 240-W prototype LLC resonant converter operating at 1-MHz switching frequency.]]>3210777077821479<![CDATA[Dynamic Response Improvements of Parallel-Connected Bidirectional DC–DC Converters for Electrical Drive Powered by Low-Voltage Battery Employing Optimized Feedforward Control]]>3210778377941820<![CDATA[An Asymmetric Half-Bridge Resonant Converter Having a Reduced Conduction Loss for DC/DC Power Applications With a Wide Range of Low Input Voltage]]>V_{DC} input and 300 W (12 V/25 A) output.]]>3210779578043249<![CDATA[Quasi-Parallel Voltage Regulator Topology for Powering Laptop Processors]]>3210780578151511<![CDATA[Effects of Auxiliary-Source Connections in Multichip Power Module]]>mosfets or insulated gate bipolar transistor (IGBTs). This paper investigates the operation mechanism of the auxiliary-source connections in multichip power modules. It reveals that the auxiliary-source connections cannot fully decouple the power loop and the gate loop such as the Kelvin-source connection, owing to their involvement in the loop of the power source current. Three effects of the auxiliary-source connections are then analyzed, which are 1) the common source stray inductance reduction, 2) the transient drain–source current imbalance mitigation, and 3) the influence on the steady-state current distribution. Finally, simulations and experimental results validate the theoretical analysis.]]>3210781678231107<![CDATA[A Unified Analysis of the Fault Tolerance Capability in Six-Phase Induction Motor Drives]]>3210782478362344<![CDATA[Sizing of Energy System of a Hybrid Lithium Battery RTG Crane]]>321078377844724<![CDATA[Modified High-Power Nanosecond Marx Generator Prevents Destructive Current Filamentation]]>traditional Marx circuit (TMC) based on avalanche transistors with a shortened emitter and a base was investigated numerically by using a two-dimensional (2-D) physics-based approach and experimentally, and compared with a special Marx circuit (SMC) suggested here, in which an intrinsic base triggering of all the stages protects the transistors, especially the second one, from thermal destruction due to current filamentation. This is because the entire emitter–base perimeter in the SMC participates in switching, whereas in a TMC the switching is initiated across the entire area of the emitter but then changes to current filamentation due to certain 3-D transient effects reported earlier. Very significant difference in local transient overheating in the transistors operating in TMC and SMC determines the difference in reliability of those two pulse generators. The results suggest a new circuit design for improving reliability and explain the difference in the operating mode of different transistors in the chain which makes the second transistor most prone to destructive thermal filamentation. This new understanding points additionally to ways of optimizing the design of the transistors to be used in a Marx circuit.]]>321078457850555<![CDATA[Smart Electrical Grid Interface Using Floating H-Bridges to Improve the Performance of Induction Motors]]>3210785178611297<![CDATA[Pole-Phase Modulated Multiphase Induction Motor Drive With Reduced Torque Ripple and Improved DC Link Utilization]]>3210786278691039<![CDATA[Windowed SHE-PWM of Interleaved Four-Quadrant Converters for Resonance Suppression in Traction Power Supply Systems]]>3210787078812345<![CDATA[New Passive Filter Design Method for Overvoltage Suppression and Bearing Currents Mitigation in a Long Cable Based PWM Inverter-Fed Motor Drive System]]>v /dt PWM pulses induce overvoltage spikes on the motor via long cable. Such phenomenon would cause serious deterioration of the motor and cable. A passive overvoltage suppression technique of low-loss “RL-plus-C” filter was proposed recently. It has not only some merits of simple structure, low cost, and good robustness, but also a significant merit of low power dissipation. In order to further mitigate the bearing currents, this paper proposes two new power filters and their design method. The theoretical analysis and the design method are introduced in detail. Experimental results are in good agreement with the theoretical analysis.]]>3210788278931991<![CDATA[Fault-Tolerant Control of Six-Phase Induction Motor Drives With Variable Current Injection]]>3210789479031239<![CDATA[A Three-Vector Modulation Strategy for Indirect Matrix Converter Fed Open-End Load to Reduce Common-Mode Voltage With Improved Output Performance]]>3210790479152794<![CDATA[Influence of Material Properties and Geometric Shape of Magnetic Cores on Acoustic Noise Emission of Medium-Frequency Transformers]]>3210791679313518<![CDATA[A Single-Stage Single-Switch Soft-Switching Power-Factor-Correction LED Driver]]>3210793279401006<![CDATA[A Cost-Effective Zero-Voltage Switching Dual-Output LED Driver]]>3210794179531906<![CDATA[An Investigation of Temperature-Sensitive Electrical Parameters for SiC Power MOSFETs]]>dI_{DS}/dt) coupled with the gate current plateau (I_{GP}) during turn-ON could be an effective TSEP under specific operating conditions. Both parameters increase with the junction temperature of the device as a result of the negative temperature coefficient of the threshold voltage. The temperature dependency of dI_{DS}/dt has been shown to increase with the device current rating (due to larger input capacitance) and external gate resistance ($R_{G}^{\rm EXT}$). However, as dI_{DS}/dt is increased by using a small $R_{G}^{\rm EXT}$, parasitic inductance suppresses the temperature sensitivity of the drain and gate current transients by reducing the “effective gate voltage” on the device. Since the temperature sensitivity of dI_{DS}/dt is at the highest with maximum $R_{G}^{\rm EXT}$, there is a penalty from higher switching losses when this method is used in real time for junction temperature sensing. This paper investigates and models the temperature dependency of the gate and drain current transients as potential TSEPs for SiC power MOSFETs.]]>3210795479661579<![CDATA[High-Temperature Electrical and Thermal Aging Performance and Application Considerations for SiC Power DMOSFETs]]>mosfets have been measured. On-state resistances increased to 6 or 7 times their room temperature values at 350 °C. Threshold voltages almost doubled after tens of minutes of positive gate voltage stressing at 300 °C, but approached their original values again after only one or two minutes of negative gate bias stressing. Fortunately, the change in drain current due to these threshold instabilities was almost negligible. However, the threshold approaches zero volts at high temperatures after a high temperature negative gate bias stress. The zero gate bias leakage is low until the threshold voltage reduces to approximately 150 mV, where-after the leakage increases exponentially. Thermal aging tests demonstrated a sudden change from linear to nonlinear output characteristics after 24–100 h air storage at 300 °C and after 570–1000 h in N2 atmosphere. We attribute this to nickel oxide growth on the drain contact metallization which forms a heterojunction p-n diode with the SiC substrate. It was determined that these state-of-the-art SiC mosfet devices may be operated in real applications at temperatures far exceeding their rated operating temperatures.]]>3210796779791425<![CDATA[Multifault Tolerance Strategy for Three-Phase Multilevel Converters Based on a Half-Wave Symmetrical Selective Harmonic Elimination Technique]]>3210798079895158<![CDATA[Reliability Improvement of Power Converters by Means of Condition Monitoring of IGBT Modules]]>321079907997959<![CDATA[Synchronization of the Carrier Wave of Parallel Three-Phase Inverters With Virtual Oscillator Control]]>3210799880071344<![CDATA[Digital Implementation of Soft Start-Up and Short-Circuit Protection for High-Frequency LLC Converters With Optimal Trajectory Control (OTC)]]>LLC converters by using low-cost microcontrollers (MCUs) with minimum stresses and optimal energy delivery. Our current understanding of the relationship between the switching frequency and the output voltage is based on the state-plane analysis, and the requirement for the controllers is significantly reduced when using the lookup table. Further improvement enables the application of the proposed control method to high-frequency LLC converters without increasing the cost for the controllers. This paper proposes a method to protect the LLC converter from abrupt short-circuit with low-cost MCUs, which improves transient response to short-circuit significantly, and investigates limitations when operating the high-frequency LLC converter under short-circuit conditions. The proposed methods minimize the CPU resource requirement and can be further integrated with other state-trajectory control functions within one MCU. Experimental results are demonstrated on a 500-kHz 1-kW 400-V/12-V LLC converter with 60-MHz MCU TMS320F28027.]]>3210800880171329<![CDATA[Computationally Efficient DMPC for Three-Level NPC Back-to-Back Converters in Wind Turbine Systems With PMSG]]>not be feasible. In this paper, two computationally efficient DMPC schemes with hexagon candidate region (HCR) and triangle candidate region (TCR) for torque and power control of three-level neutral-point clamped back-to-back converters in wind turbine systems with permanent-magnet synchronous generator are proposed. By an appropriate selection of the candidate regions, the number of reasonable switching states is drastically reduced which saves computation time up to 55% for HCR and up to 83% for TCR, respectively. The computational efficiency improvements and the control performances of the proposed DMPC schemes are compared and validated by real-time implementations on an field programmable gate array (FPGA) system and by measurement results at a lab-constructed test bench. The achieved control performance of the proposed methods is comparable with that of the classical DMPC, while the computation times are drastically reduced.]]>3210801880343135<![CDATA[Triple Phase Shift Control of an LLL Tank Based Bidirectional Dual Active Bridge Converter]]>mosfets for the entire operating range. Experimental results confirm complete ZVS of all mosfets under various voltage gains and load conditions. A comparative loss breakdown for the TPS-controlled LLL tank VF-DAB and the conventional inductive link VF-DAB at various operating conditions show the necessity of the additional auxiliary inductors in the conventional design for increasing optimal switching frequency of the IBDC.]]>3210803580538768<![CDATA[Wide-Range Adaptive IPT Using Dipole-Coils With a Reflector by Variable Switched Capacitance]]>3210805480705893<![CDATA[Hot-Swapping Analysis and Implementation of Series-Stacked Server Power Delivery Architectures]]>3210807180884495<![CDATA[Synchronverter-Enabled DC Power Sharing Approach for LVDC Microgrids]]>3210808980992507<![CDATA[Discrete-Time Domain Modeling of Voltage Source Inverters in Standalone Applications: Enhancement of Regulators Performance by Means of Smith Predictor]]> LC plant with consideration of delay and sample-and-hold effects on the state feedback cross-coupling decoupling is derived. From this plant formulation, current controllers with wide bandwidth and good relative stability properties are developed. Two controllers based on lead compensation and Smith predictor design, respectively, are obtained. Subsequently, the voltage regulator is also designed for a wide bandwidth, which permits the inclusion of resonant filters for the steady-state mitigation of odd harmonics at nonlinear unbalance load terminals. Discrete-time domain implementation issues of an antiwind up scheme are discussed as well, highlighting the limitations of some discretization methods. Extensive experimental results, including a short-circuit test, verify the theoretical analysis.]]>3210810081144506<![CDATA[Capacitor Voltages Measurement and Balancing in Flying Capacitor Multilevel Converters Utilizing a Single Voltage Sensor]]>3210811581231503<![CDATA[A Novel Adaptive Quasi-Constant On-Time Current-Mode Buck Converter]]>[1]–[5] . In this paper, a novel adaptive quasi-constant on-time current-mode control scheme is proposed and implemented in buck converters. While preserving the advantages of the conventional COT current-mode converters, this scheme allows fast transient response to step-load that is a critical requirement of a computer load with smart management. A small-signal model of the proposed circuit is also developed. Experimental results are also provided. This scheme is well suited for the next-generation dc converters for power management central-processor-unit devices.]]>3210812481331380<![CDATA[Analysis and Dynamic Performance Improvement of Grid-Connected Voltage–Source Converters Under Unbalanced Network Conditions]]>3210813481498107<![CDATA[Reducing the Inductors of Rectifiers Having Two Outputs to Improve Power Density]]>3210815081621846<![CDATA[Modified Cascaded Boundary-Deadbeat Control for a Virtually-Grounded Three-Phase Grid-Connected Inverter With LCL Filter]]>LCL output filter. Such architecture mitigates filter resonance and offers good stability under stiff- and weak-grid conditions. However, its merits are offset by requiring many sensors, dedicated control loop to regulate the operating frequency, and high-precision intracycle information of the circuit variables to dictate the states of the switches. A modified cascaded boundary-deadbeat control law with reduced number of current sensors, the use of current band to regulate the operating frequency, and intracycle information recovery mechanism of the filter capacitor voltage for a virtually-grounded three-phase grid-connected inverter with LCL filter is presented. It inherits the merits of allowing the inverter to exhibit fast dynamic response and mitigating filter resonance. The contaminated intracycle information of the filter capacitor voltage is recovered so as to estimate and predict state trajectories accurately. Furthermore, a dc bus voltage feedforward injection scheme with reduced number of voltage sensor is proposed. It utilizes the duty cycle information of the gate signals to compensate the effect of the unbalanced dc bus capacitor voltages on causing modulation saturation and current distortion. The system characteristics under parametric variations will be studied. A 3-kW prototype has been built and evaluated under stiff- and weak-grid conditions.]]>3210816381803613<![CDATA[A Novel Source Current Control Strategy and Its Stability Analysis for an Indirect Matrix Converter]]>d-axis dc component, and the quality of the source current can be improved by suppressing the harmonics. On the basis of above analysis, a novel source current control strategy is proposed for an IMC with asymmetric modulation, which can improve the source current quality and correct the input power factor. Self-tuning resonant controllers and a proportional integral controller are employed to achieve above goals. The stability of the system is also analyzed considering the change of input impendence after adding the source current control, which can be used as the guidance for the selection of control parameters. Finally, the validity and the feasibility of the control strategy are verified via experiments.]]>3210818181922528<![CDATA[Transient Control of the Reactive Current for the Line-Side Converter of the Brushless Doubly-Fed Induction Generator in Stand-Alone Operation]]>3210819382031507<![CDATA[Impact of Power Flow Direction on the Stability of VSC-HVDC Seen From the Impedance Nyquist Plot]]>3210820482172992<![CDATA[A Root-Locus Design Methodology Derived From the Impedance/Admittance Stability Formulation and Its Application for LCL Grid-Connected Converters in Wind Turbines]]>LCL grid-connected converters for wind turbine applications. The design target is formulated as a minimization of the current loop dominant time constant, which is in accordance with standard design guidelines for wind turbine controllers (fast time response and high stability margins). The proposed approach is derived from the impedance/admittance stability formulation, which, on one hand, has been proved to be suitable for the controller design when the active damping is implemented and, on the other hand, has also been proved to be very suitable for system-level studies in applications with a high penetration of renewable energy resources. The tuning methodology is as follows: first, the physical system is modeled in terms of the converter admittance and its equivalent grid impedance; then, a sensitivity transfer function is derived, from which the closed-loop eigenvalues can be calculated; finally, the set of control gains that minimize the dominant time constant are obtained by direct search optimization. A case study that models the target system in a low-power scale is provided, and experimental verification validates the theoretical analysis. More specifically, it has been found that the solution that solves the minimization of the current controller time constant (wind turbine controller target) also corresponds to a highly damped electrical response (robustness provided by the active damping).]]>3210821882281011<![CDATA[IEEE Power Electronics Society]]>3210C3C352