<![CDATA[ IEEE Transactions on Power Electronics - new TOC ]]>
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TOC Alert for Publication# 63 2018February 22<![CDATA[Table of Contents]]>336C1457058<![CDATA[IEEE Power Electronics Society]]>336C2C262<![CDATA[Sideband Harmonic Instability of Paralleled Inverters With Asynchronous Carriers]]>336457145772362<![CDATA[Optimized Branch Current Control of Modular Multilevel Matrix Converters Under Branch Fault Conditions]]>336457845833854<![CDATA[Multiple-Phase-Shift Control for a Dual Active Bridge to Secure Zero-Voltage Switching and Enhance Light-Load Performance]]>33645844588808<![CDATA[EMI Noise Separation Method for Three-Phase WBG Inverters With Low Sensitivity to Parasitic Parameters]]>33645894593821<![CDATA[An Interleaved PWM Method With Better Voltage-Balancing Ability for Half-Bridge Three-Level DC/DC Converter]]>33645944598949<![CDATA[Closed-Form Solution for Core Loss Calculation in Single-Phase Bridgeless PFC Rectifiers Based on the iGSE Method]]>B–H curve. However, the computational procedure based on loop separation routine of the iGSE is replaced here with an integral-based computation. This leads to the advantage that the resulting expressions are in a closed form that is suitable for optimization routines. The proposed method can be extended to other converters. Three different design results are compared with two standard numerical iGSE routines, one made by the authors and the original routine made by the iGSE authors. Experimental results for a fourth case are presented. The importance of modeling the major loop losses is also discussed.]]>33645994604447<![CDATA[A Damping Scheme for Switching Ringing of Full SiC MOSFET by Air Core PCB Circuit]]>mosfet is proposed. It reveals that the ringing phenomenon caused by parasitic impedances of switching circuit can be damped out using air core PCB transformer which has a properly designed secondary side circuit. The design method for PCB transformer and the secondary circuit are developed considering the physical dimension applied to the PCB transformer inserted between full SiC mosfet module and snubber capacitor. Experimental results using 1200 V–180 A full SiC mosfet module validate the design method and the performance of the proposed air core PCB circuit. Thanks to the damping circuit, the resonant component due to the switching ringing has been reduced to a half compared to that of system without damping circuit.]]>336460546154773<![CDATA[Optimal Design of Integrated Magnetics for Differential Rectifiers and Inverters]]>336461646261548<![CDATA[Train–Network Interactions and Stability Evaluation in High-Speed Railways–Part I: Phenomena and Modeling]]>DQ-domain. The entire traction network, including traction transformer, catenary, supply lines, is represented in a frequency-domain nodal matrix. Furthermore, the impedance–frequency responses of both electric train and traction network are measured and validated through frequency scan method. Finally, a generalized train–network simulation and experimental system are conducted for verifying the theoretical results of the two-part paper.]]>336462746422812<![CDATA[Train–Network Interactions and Stability Evaluation in High-Speed Railways—Part II: Influential Factors and Verifications]]>336464346594920<![CDATA[Large-Scale Nonlinear Device-Level Power Electronic Circuit Simulation on Massively Parallel Graphics Processing Architectures]]>336466046785425<![CDATA[Wireless Power and Bidirectional Data Transfer Scheme for Battery Charger]]>LC tank. The primary unit employs an inverter to yield alternating current and power flow to the load via mutual inductance. The secondary unit transfers data by adjusting current of load, and the primary unit receives data based on the zero-voltage switching method. The primary unit transfers command by trimming the current's curve and the secondary unit receives command and make decoding using the period of carrier wave. It is worth to mention that the design scheme enables it to handle the situation of emergency by sending back the message to the primary unit to make an emergency halt.]]>336467946892033<![CDATA[Topology and Control of a Five-Level Hybrid-Clamped Converter for Medium-Voltage High-Power Conversions]]>336469047022485<![CDATA[Modulation and Control of a Three-Phase Phase-Modular Isolated Matrix-Type PFC Rectifier]]> $Delta$) configuration, enabling a wide input voltage range. Additionally this allows to select the voltage and current stresses of the phase module switches according to the used semiconductor technology, for example ${text{650 V}}$ Si or GaN devices could be used in rectifiers powered from the ${400}$ or ${text{480 V}}_{text{rms}}$ mains. A detailed analysis of the operating principles and switching behavior of the converter is presented, showing that zero voltage switching can be achieved in the phase modules. Additionally a third harmonic current injection concept is proposed which allows an up to ${15} %$ higher output voltage in $Delta$-mode. The concepts are validated with measurements taken on a ${text{7.5}};{text{kW}}$, ${text{400}};{text{V}}$ dc output voltage prototype converter achieving ${97.2} %$ efficiency and a total harmonic distortion of $ < {2} %$ at rated power.]]>336470347152445<![CDATA[A Three-Phase Integrated Onboard Charger for Plug-In Electric Vehicles]]>336471647251445<![CDATA[DC Capacitor Voltage Balancing Control for Delta-Connected Cascaded H-Bridge STATCOM Considering Unbalanced Grid and Load Conditions]]>336472647353016<![CDATA[Analytical Technique for Designing an RC Snubber Circuit for Ringing Suppression in a Phase-Leg Configuration]]>RC) snubber circuit for suppressing ringing in phase-leg configurations that are among the main components in electric power converters. In our study, a double pulse circuit is used to examine the effects of RC snubber circuit ringing suppression because the phase-leg and double pulse configuration ringing mechanisms are the same. First, a high-frequency equivalent circuit of the double pulse circuit is derived. Next, an RC snubber circuit for ringing suppression is analytically designed by scrutinizing the characteristic equations via the root locus method. Prior to using the root locus method, we conducted an investigation to determine if that method could be used to analyze the derived high-frequency equivalent circuit when RC snubber circuit parasitic inductances and inductances between the upper and lower modules connectors are small enough to ignore. Finally, the ringing suppression effect of the RC snubber designed by using the proposed analytical technique in a double pulse circuit with practical parasitic inductance values is confirmed via circuit simulations and experimental demonstrations.]]>336473647451608<![CDATA[Operation and Control Strategy of a New Hybrid ESS-UPS System]]>336474647557610<![CDATA[An Enhanced Steady-State Model and Capacitor Sizing Method for Modular Multilevel Converters for HVdc Applications]]>336475647711610<![CDATA[New Modulated Carrier Controlled PFC Boost Converter]]>336477247822589<![CDATA[A 500-kHz, 3.3-kW Power Factor Correction Circuit With Low-Loss Auxiliary ZVT Circuit]]>mosfet, and a diode. This inductor resonates with the capacitances of the main mosfet and main diode during the turn-on transition to achieve zero-voltage switching, whereas the auxiliary mosfet itself turns off with zero-current switching. The conduction time of the auxiliary circuit is very small compared to the switching period of the main boost converter, and hence it processes only a small fraction of the output power. This allows efficient operation of the boost converter even while using Silicon mosfets at relatively high switching frequencies. A discharge mechanism comprising of a capacitor and low-frequency diode helps transfer the energy processed in the auxiliary circuit to the output. The proposed ZVT circuit has no effect on the control scheme of the main PFC, and is easy to implement with a digital processor. The operating principles, waveforms in different intervals, and the design of the auxiliary ZVT circuit are presented in detail. Some extensions of the proposed concept in terms of different discharge mechanisms and coupled-inductor implementations are also discussed. The analysis and performance of PFC with ZVT circuit and its benefits are validated through extensive simulation and experimental results from a 3.3-kW/500-kHz hardware prototype.]]>336478347951847<![CDATA[Performance of a Distributed Dynamic Brake for an Induction Motor Fed by a Modular Multilevel DSCC Inverter]]>336479648063777<![CDATA[Analysis, Design, and Implementation of a High Gain Soft-Switching Bidirectional DC–DC Converter With PPS Control]]>336480748161523<![CDATA[Hybrid Microgrid With Parallel- and Series-Connected Microconverters]]>336481748314536<![CDATA[A Two Degrees of Freedom Resonant Control Scheme for Voltage-Sag Compensation in Dynamic Voltage Restorers]]>$alpha text{--}beta$), with two nested controllers used to obtain a passband behavior of the closed-loop transfer function, and is capable of achieving both a balanced and an unbalanced voltage-sag compensation. The 2DOF control has certain advantages with regard to traditional control methods, such as the possibility of ensuring that all the poles of the closed-loop transfer function are chosen without the need for observers and reducing the number of variables to be measured. The use of the well-known double control-loop schemes that employ feedback current controllers to reduce the resonance of the plant is, therefore, unnecessary. A simple control methodology permits the dynamic behavior of the system to be controlled and completely defines the location of the poles. Furthermore, extensive simulations and experimental results obtained using a 5-kW DVR laboratory prototype show the good performance of the proposed control strategy.]]>336485248672553<![CDATA[Three-Phase Transformerless Shunt Active Power Filter With Reduced Switch Count for Harmonic Compensation in Grid-Connected Applications]]>LC PFs. The third leg of the three-phase VSI is removed by eliminating the set of power switching devices, thereby directly connecting the phase with the negative terminals of the dc-link capacitor. The proposed topology enhances the harmonic compensation capability and provides complete reactive power compensation compared with conventional APF topologies. The new experimental prototype is tested in the laboratory to verify the results in terms of total harmonic distortion, balanced supply current, and harmonic compensation, following the IEEE-519 standard.]]>336486848813374<![CDATA[Single-Phase Converter With Shared Leg and Generalizations]]> $N_{text{leg}}$ legs. The first generalization is the cascaded shared leg (CSL), where the converter is cascaded by $N_{text{leg}}-1$ transformers, and one of the $N_{text{leg}}$ legs is shared between all transformers. The second is the modular CSL, where $N_{rm mod}$ modules, each one similar to the basic configuration, are cascaded by $2N_{rm mod}$ transformers. The conventional configurations considered for general comparisons are the cascaded h-bridge (CHB) and the cascaded half-bridge (CHfB). In this paper, we show that proposed configurations provide multilevel ac voltages with greater levels-per-switch ratio compared to the CHB. We also show that proposed CSL generalization has practically the same levels-per-switch than conventional CHfB and saves one transformer. Simulations and experimental results are shown to demonstrate proposed configurations performance and feasibility.]]>336488248931546<![CDATA[An LCC-C Compensated Wireless Charging System for Implantable Cardiac Pacemakers: Theory, Experiment, and Safety Evaluation]]>LCC-C compensation topology for pacemaker wireless charger is presented, where only one secondary side resonance capacitor needs to be implanted, and resonance compensation parameters are derived. The compensation network can make the WPT system operate at stable resonance and high efficiency. The prototype of the wireless charging system for implantable cardiac pacemaker is developed, where a thin flexible receiving unit was designed to effectively shield eddy currents in the pacemaker shell. The experiments of wireless charging through pork tissues reveal that 3.072-W power can be received from a 3.919-W power source at 300 kHz, reaching a rather high WPT efficiency of 78.4%, such that the charging is fast, i.e., the 1050 mA·h, 4.2-V Li-ion battery voltage increases from 3.98 (80% residual capacity) to 4.2 V within only 27 min, and only 3.3 °C maximum temperature rise of the pork is in safe limits. The feasibility and safety of the charging system were further evaluated by simulations of specific absorption rate and temperature rise in human tissues and electromagnetic fields in the pacemaker case.]]>33648944905905<![CDATA[A Simple Smooth Transition Technique for the Noninverting Buck–Boost Converter]]>336490649151863<![CDATA[Naturally Adaptive, Low-Loss Zero-Voltage-Transition Circuit for High-Frequency Full-Bridge Inverters With Hybrid PWM]]>336491649333143<![CDATA[Sequence Domain Harmonic Modeling of Type-IV Wind Turbines]]>336493449431154<![CDATA[Systematic Design of the Hybrid Damping Method for Three-Phase Inverters With High-Order Filters]]>High-order filters (HO-filters) such as LCL-LC-filters have recently drawn attention to their small size and better attenuation to switching harmonics than LCL -filters for three-phase inverter grid interfaces. Hybrid damping that combines passive damping and active damping is an effective method to suppress HO-filter resonances. However, due to the high-order characteristic of the system, the tuning procedure for the parameters of hybrid damping is complicated. Hence, an equivalent circuit analysis method is proposed in this paper to accurately simplify the model of the HO-filter. Based on this, a systematic step-by-step design method for HO-filter-type grid-connected inverters with hybrid damping has been proposed. The passive losses, effects of equivalent series resistances (ESRs) and robustness against grid impedance variation have been studied. Compared with existing design procedures, the proposed method makes the hybrid damping more reliable by locating appropriate position for closed-loop resonant poles. Experimental results verify the proposed systematic design procedure.]]>336494449562385<![CDATA[Two-Transmitter Wireless Power Transfer with Optimal Activation and Current Selection of Transmitters]]>336495749671294<![CDATA[A Novel Reversal Coupled Inductor High-Conversion-Ratio Bidirectional DC–DC Converter]]>336496849792487<![CDATA[An Inductive and Capacitive Combined Parallel Transmission of Power and Data for Wireless Power Transfer Systems]]>336498049911423<![CDATA[Development of DC to Single-Phase AC Voltage Source Inverter With Active Power Decoupling Based on Flying Capacitor DC/DC Converter]]>3) among the topologies considered herein.]]>336499250042813<![CDATA[Maximum Efficiency Tracking for Wireless Power Transfer Systems With Dynamic Coupling Coefficient Estimation]]>336500550151455<![CDATA[Low-Power Multichannel Wireless Transmitter]]>336501650281872<![CDATA[Transmitter Coil Resonant Frequency Selection for Wireless Power Transfer]]>336502950411704<![CDATA[An Independently Controlled Single-PWM Multiple-Output Narrow-Band Resonant Converter]]>336504250612248<![CDATA[Analysis and Design of High-Frequency Converter With Resistive Matching Network and Spiral Inductor]]>336506250752730<![CDATA[A Single-Phase PFC Rectifier With Wide Output Voltage and Low-Frequency Ripple Power Decoupling]]>336507650865428<![CDATA[A Low-Stress Zero-Current Switching Technique for Power Converters]]>C_{oss} of the auxiliary switch, which does not have the negative impact in zero-voltage switching (ZVS) converters. This paper proposes a low-stress ZCS technique to eliminate the negative consequence of the C_{oss} in ZCS PWM converters. All the power devices, including the auxiliary switch, show low voltage stresses and ZCS. The auxiliary cell of the low-stress ZCS technique introduced a clamping diode to realize the low-voltage stress for the power devices. The low-stress ZCS buck converter is taken as an example to explain both the low-stress and ZCS characteristics. A 2-kW hardware prototype is developed. The simulation and experiment results both validate the effectiveness of the proposed low-stress ZCS technique.]]>336508750961269<![CDATA[CCM Noninverting Buck–Boost Converter With Fast Duty-Cycle Calculation Control for Line Transient Improvement]]>336509751071600<![CDATA[An Integrated DC–DC Boost Converter Having Low-Output Ripple Suitable for Analog Applications]]>L–C filter, which drastically reduces the output ripple. The L–C filter has been realized using 30-nH bondwire inductance and 0.54-nF on-chip capacitance. The converter switches at 118 MHz and produces a regulated 3.2-V output from an input voltage ranging from 1.0 to 2.7 V. The converter is able to deliver up to 65-mA current for input voltage $geq$ 2.4 V. The prototype has been implemented in 0.18-$mu$m standard digital CMOS process and the entire design consumes only 0.52-mm$^2$ chip area resulting in a maximum power density of 0.387 W/mm$^2$. Peak efficiency of the converter is 77.4% at 32.2-mA current for 2.7-V input supply. The measured maximum output ripple noise is 21 mV that is less than 0.65% of the regulated output voltage.]]>336510851171702<![CDATA[Single-Phase Hybrid Switched-Capacitor Voltage-Doubler SEPIC PFC Rectifiers]]>336511851302402<![CDATA[An Improved Rotor Flux Space Vector Based MRAS for Field-Oriented Control of Induction Motor Drives]]> ${vec{V}^ * } times vec{I}$ based MRAS in MATLAB/ Simulink. Stability and sensitivity studies are further carried out to ensure the robustness of the drive system. Experimental results as obtained by a dSPACE-1104 based IM laboratory prototype are also presented to validate the simulation study.]]>336513151412112<![CDATA[A Dual Modular Multilevel Converter With High-Frequency Magnetic Links Between Submodules for MV Open-End Stator Winding Machine Drives]]>3365142515919441<![CDATA[Trajectory Optimization for Loss Minimization in Induction Motor Fed Elevator Systems]]>336516051701352<![CDATA[DC-Link Current and Voltage Ripple Analysis Considering Antiparallel Diode Reverse Recovery in Voltage Source Inverters]]>$pm$5% and increased by up to 7% compared with the existing method neglecting the antiparallel diode reverse recovery.]]>336517151803188<![CDATA[Practical Testing Solutions to Optimal Stator Harmonic Current Design for PMSM Torque Ripple Minimization Using Speed Harmonics]]>336518151915266<![CDATA[Optimized Design of a High Input-Voltage-Ripple-Rejection Converter for LED Lighting]]>336519252051249<![CDATA[Investigation of the Active Ripple Compensation Technique to Reduce Bulk Capacitance in Offline Flyback-Based LED Drivers]]>336520652142336<![CDATA[Assessment of 10 kV, 100 A Silicon Carbide <sc>mosfet</sc> Power Modules]]>mosfet power modules, equipped with third-generation mosfet chips and without external free-wheeling diodes, using the inherent SiC mosfet body-diode instead. The static performance (e.g., I_{DS}–V_{DS }, I_{DS}–V_{GS}, C–V characteristics, leakage current, body-diode characteristics) is addressed by measurements at various temperatures. Moreover, the power module is tested in a simple chopper circuit with inductive load to assess the dynamic characteristics up to 7 kV and 120 A. The SiC mosfet power module exhibits an on-state resistance of 40 mΩ at room-temperature and leakage current in the range of 100 nA, approximately one order of magnitude lower than that of a 6.5 kV Si-IGBT. The power module shows fast switching characteristics with the turn-on (turn-on loss) and turn-off (turn-off loss) times of 130 ns (89 mJ) and 145 ns (33 mJ), respectively, at 6.0 kV supply voltage and 100 A current. Furthermore, a peak short-circuit current of 900 A and a short-circuit survivability time of 3.5 μs were observed. The extracted characterization results could serve as input for power electronic converter design and may support topology evaluation with realistic system performance predictability, using SiC mosfet power modules in the energy transmission and distribution networks.]]>336521552254379<![CDATA[Tradeoff Study of Heat Sink and Output Filter Volume in a GaN HEMT Based Single-Phase Inverter]]>LC output filter volume are presented with respect to experimental results of the single phase prototype. The findings from static, dynamic characterization, and single phase prototype results clearly show that GaN HEMT has excellent switching performance under wide load current and heat sink temperature conditions. The high performance of the inverter leads to reduction of the combined total volume, including output filter and heat sink volume.]]>336522652392507<![CDATA[Accurate Transient Calorimetric Measurement of Soft-Switching Losses of 10-kV SiC mosfets and Diodes]]>mosfets is a difficult but necessary task in order to provide a sound basis for the accurate modeling of converter systems, such as medium-voltage-connected solid-state transformers, where soft-switching techniques are employed to achieve an improved converter efficiency. Switching losses (SL), in general, are typically measured with the well-known double pulse method. In the case of SSL measurements, however, this method is very sensitive to the limited accuracy of the measurement of the current and voltage transients, and thus is unsuitable for the characterization of fast-switching high-voltage mosfets. This paper presents an accurate and reliable calorimetric method for the determination of SSL using the example of 10-kV SiC mosfet modules. Measured SSL curves are presented for different dc-link voltages and switched currents. Furthermore, a deeper analysis concerning the origin of SSL is performed. With the proposed measurement method, it can be experimentally proven that the largest share of the SSL arises from charging and discharging the output capacitance of the mosfet module and especially of the antiparallel junction barrier Schottky diode.]]>336524052504144<![CDATA[A Deep Insight Into the Degradation of 1.2-kV 4H-SiC mosfets Under Repetitive Unclamped Inductive Switching Stresses]]>mofsets under repetitive unclamped inductive switching stresses is evaluated experimentally. The degradation of device characteristics, including the threshold voltage $V_{{rm{th}}}$, drain leakage current $I_{{rm{dss}}}$, and on-state resistance $R_{{rm{on}}}$, is observed after 80k avalanche cycles. The regular charge pumping (CP) measurements reveal that the failure mechanism characterized by the hot holes injection and trapping into the gate oxide above the channel and JFET region may occur during the aging experiments, which is further ascertained by the succeeding electrothermal simulations and should be responsible for the degradation of $V_{{rm{th}}}$ and $I_{{rm{dss}}}$. After decapping the failed devices, the bond wires lift off due to thermal fatigue is discovered and regarded as the main reason for the degradation of $R_{{rm{on}}}$. The poststress high-temperature treatment is also carried out as an approach to indirectly corroborate the aforementioned failure mechanisms. Moreover, the impact of different test conditions on the degradation rate of electrical characteristics is discussed to thereby find ways to relieve these degeneration phenomena.]]>336525152611686<![CDATA[Characterisation and Modeling of Gallium Nitride Power Semiconductor Devices Dynamic On-State Resistance]]>$R_mathrm{DS(on)}$) above its theoretical value. This increase is a function of the applied dc bias when the device is in its off state, and the time which the device is biased for. Thus, dynamic $R_mathrm{DS(on)}$ of different commercial GaN-HEMTs are characterised at different bias voltages in the paper by a proposed new measurement circuit. The time-constants associated with trapping and detrapping effects in the device are extracted using the proposed circuit and it is shown that variations in $R_mathrm{DS(on)}$ can be predicted using a series of RC circuit networks. A new methodology for integrating these $R_mathrm{DS(on)}$ predictions into existing gallium nitride-high-electron-mobility transistors models in standard SPICE simulators to improve model accuracy is then presented. Finally, device dynamic $R_mathrm{DS(on)}$ values of the model is compared and validated with the measurement when it switches in a power converter with different duty cycles and switching voltages.]]>336526252731639<![CDATA[Junction Temperature Measurement Method for Power mosfets Using Turn-On Delay of Impulse Signal]]>mosfets). The measurement method is using the turn-on delay of impulse signal, which is the delay time between the rising edge of impulse signal and the corresponding rising edge of drain–source current. Results show that the turn-on delay has a good linear relationship with temperature, and the method is suitably efficient for accurate junction temperature measurement of power mosfet s. The proposed method is verified using the thermal infrared method. Finally, this method is used to measure the real-time junction temperature of power mosfet device in a dc–dc boost converter.]]>336527452824601<![CDATA[Quasi-Online Technique for Health Monitoring of Capacitor in Single-Phase Solar Inverter]]>336528352911022<![CDATA[New Analytical Model for Real-Time Junction Temperature Estimation of Multichip Power Module Used in a Motor Drive]]>336529253011140<![CDATA[Modeling and Analysis of a Dual-Active-Bridge-Isolated Bidirectional DC/DC Converter to Minimize RMS Current With Whole Operating Range]]>336530253166061<![CDATA[Low-Cost Maximum Efficiency Tracking Method For Wireless Power Transfer Systems]]>$dD/d{V_{{text{in}}}}$ ( ${V_{{text{in}}}}$ being the inverter's dc input and $D$ being the duty cycle of the converter) is equal to or smaller than a constant $beta $ that is determined by system parameters. By tuning ${V_{{text{in}}}}$ and comparing $dD/d{V_{{text{in}}}}$ with $beta $, the MEP can be tracked without a power or current sensor, hence reducing the tracking cost. A WPT system is demonstrated experimentally to verify the method. When the diameters of and the vertical distance between the transmitting and receiving coils are 4.3 and 2.35 cm, respectively, without horizontal misalignment, high efficiency is maintained even when the load ranges from 5 to 100 Ω, and the efficiency improvement reaches 41.2% when compared to the measured efficiencies without the proposed method. The differences between the maximum efficiencies tracked by the proposed method and the manually searched maximum values are at most 1.8%. Extension of the proposed method to WPT systems employing other popular forms of inverter, dc/dc converter, and coil topology is also presented.]]>336531753291213<![CDATA[A 6.78 MHz Multiple-Receiver Wireless Power Transfer System With Constant Output Voltage and Optimum Efficiency]]>336533053402437<![CDATA[Autonomous Power Management in LVDC Microgrids Based on a Superimposed Frequency Droop]]>336534153501421<![CDATA[Digital Implementation of Adaptive Synchronous Rectifier (SR) Driving Scheme for High-Frequency LLC Converters With Microcontroller]]>LLC converters in order to reduce the secondary conduction loss. Conventional SR driving schemes are not suitable for high-frequency LLC converters: the analog driving schemes will lose a large portion of duty cycle due to SR parasitic inductance; and the digital driving schemes will require a much higher cost digital controllers in high-frequency operation. In this paper, a digital implementation of adaptive SR driving scheme for high-frequency LLC converters with cost-effective microcontroller is proposed. The proposed SR driving scheme senses SR drain–source voltage in order to detect body diode conduction, and tune the SR on-time every several switching cycles using ripple (asynchronous) counter to minimize body diode conduction. The proposed digital implementation has a simple control scheme, requires only low-cost digital controllers and minimizes controller resources utilization. More importantly, to cooperate with the closed-loop control, adaptive SR driving and closed-loop control are executed synchronously and SR on-time is modified accordingly during fast transient response to guarantee safe operation. With these techniques, the proposed adaptive SR driving can be embedded into the digital controllers with little extra cost. Experimental results are demonstrated on a 500-kHz 1-kW 400 V/12 V LLC converter with a 60-MHz microcontroller and a ripple counter.]]>336535153611788<![CDATA[Positive and Negative Sequence Control Strategies to Maximize the Voltage Support in Resistive–Inductive Grids During Grid Faults]]>336536253731289<![CDATA[Optimal Dual-Phase-Shift Control Strategy of an Isolated Buck–Boost Converter With a Clamped Inductor]]>336537453859869<![CDATA[Analysis of Tan-Sun Coordinate Transformation System for Three-Phase Unbalanced Power System]]>336538654001991<![CDATA[Compensation of DC Offset and Scaling Errors in Voltage and Current Measurements of Three-Phase AC/DC Converters]]>d–q) reference frame. The proposed control algorithm is able to effectively reject the impact of both voltage and current measurement error so that the three-phase input currents are regulated to be balanced and sinusoidal with ultralow dc current component. Meanwhile, the dc output voltage is also well regulated to be pure dc with a negligibly small voltage ripple. The proposed compensation method is developed without the need of extra hardware circuit, sensor, or precise information of system parameters so that it can be considered as more cost effective and robust solution. The effectiveness of the proposed solution is verified by experimental results.]]>336540154141671<![CDATA[Quasi-Interleaved Current Control for Switch-Linear Hybrid Envelope-Tracking Power Supply]]>336541554252158<![CDATA[Robust Stability Analysis of a DC/DC Buck Converter Under Multiple Parametric Uncertainties]]>$mu$ method justifiably takes into account all possible uncertainties in the system. However, the application of the $mu$ method to power electronic systems with multiple uncertainties is not widely discussed in the literature. This paper presents practical approaches to applying the $mu$ method in the robust stability analysis of such uncertain systems. Further, it reveals the significant impact of various types of parametric uncertainties on the reliability of stability assessments of power electronic systems. This is achieved by examining the robust stability margin of the dc/dc buck converter system, when it is subject to variations in system load, line resistance, operating temperature, and uncertainties in the system model. The $mu$ predictions are supported by time-domain simulation and experimental results.]]>336542654411749<![CDATA[Optimal Perturbation Tolerance in VSC-Connected Hybrid Networks Using an Expert System on Chip]]>33654425451999<![CDATA[Improved Virtual Space Vector Modulation for Three-Level Neutral-Point-Clamped Converter With Feedback of Neutral-Point Voltage]]>k of the NP voltage imbalance is introduced. The small vector favorable to the NP voltage balance is selected based on the factor k and phase current direction to achieve precise control and balancing of NP voltage. The proposed method can effectively maintain NP voltage balance and eliminate the low frequency oscillation of the NP voltage over the whole modulation index range. The improved VSVPWM also has advantages of good dynamic performance. The method has been tested and verified by simulations and experiments.]]>336545254642614<![CDATA[Modeling and Analysis of Variable Frequency One-Cycle Control on High-Power Switched-Capacitor Converters]]>336546554751440<![CDATA[Load Current Decoupling Based LQ Control for Three-Phase Inverter]]>α and β axes as a unified system is adopted to increase the control degree of freedom. The LQ control synthesizes the state feedback control law including gains of the resonant controllers. Two general criteria, namely $H_{infty }$ norm and zero dynamic, are proposed as the design guideline for the load current decoupling control. The effectiveness and robustness of the proposed approach are validated through MATLAB/Simulink simulations and experiments with a 5-kVA testbed. The results prove that some favorable performances, for example, the fast recovering time, the small voltage drop, and the low total harmonic distortion, are achieved by the proposed approach compared to the classical dual-loop proportional-resonant (PR) control with load current decoupling and the optimal $H_{infty }$ control.]]>336547654912548<![CDATA[Pulse Density Modulation for Maximum Efficiency Point Tracking of Wireless Power Transfer Systems]]>on–off control of the transmitting side inverter and the receiving side active rectifier instead of dc/dc converters but cause new problems, e.g., hard switching, low average efficiency, and large dc voltage ripples. This paper proposes a pulse density modulation (PDM) based implementation for MEPT to eliminate all the mentioned disadvantages of existing implementations. Delta-sigma modulators are used as an example to realize the PDM. A dual-side soft switching technique is proposed for the PDM. The ripple factor of the output voltage with PDM is derived. A 50 W WPT system is built to validate the proposed method. The system efficiency is maintained higher than 70% for various load resistances when the power transfer distance is 0.5 m, which is 1.67 times the diameter of the coils.]]>336549255011676<![CDATA[On Dynamic Modeling of PCM-Controlled Converters—Buck Converter as an Example]]>336550255182632<![CDATA[Control of a Single-Phase Cascaded H-Bridge Active Rectifier Under Unbalanced Load]]>336551955271288<![CDATA[Correction to “A Robust One-Shot Switch for High-Power Pulse Applications”]]>3365528552841<![CDATA[IEEE Power Electronics Society]]>336C3C353<![CDATA[Blank page]]>336C4C42