http://ieeexplore.ieee.org TOC Alert for Publication# 6040 2009 June 19 32 2 C1 234 57 32 2 C2 C2 40 32 2 235 236 236 Improvements in signaling methods, circuits and process technology have allowed input/output (I/O) data rates to scale beyond 10 Gb/s over several legacy channels. In this regime, it is critical to accurately model and comprehend channel/circuit nonidealities in order to co-optimize the link architecture, circuits, and interconnect. Empirical and worst-case analysis methods used at lower rates are inadequate to account for several deterministic and random noise sources present in I/O links today. In this paper, we review models and methods for statistical signaling analysis of high-speed links, and also propose a new way to integrate behavioral modeling approaches with analytical methods. A computationally efficient segment-based analysis method is shown to accurately capture the effect of transmit jitter and its interaction with the channel. In addition, a new jitter interpretation approach is proposed to enable the analysis of arbitrary I/O clocking topologies. We also present some examples to illustrate the practical utility of these analysis methods in the realm of high-speed I/O design. ]]> 32 2 237 247 1658 This paper presents techniques for characterizing wide-band on-chip power supply noise using only two on-chip low-throughput samplers. The properties of supply noise and their associated measurement techniques are reviewed to show how this can be achieved. An initial design of the samplers uses high-resolution VCO-based analog-to-digital converters, and experimental results from a test-chip verify the efficacy of the measurement techniques. To enable simple sampler designs to be used even in aggressively scaled process technologies, measurement systems based on dithered low-resolution samplers are also developed and experimentally characterized. ]]> 32 2 248 259 1052 Predicting the performance of a high-speed serial link for real world application requires a different approach to simulation than that traditionally used in slower systems. Given target bit error rates of ${10}^{-12}$ and lower, the ability to statistically confirm such performance in measurement, let alone simulation is challenging. For physically realistic interconnect and feasible silicon implementations, certain assumptions allow this problem to be solved with an analytical method in the so called statistical domain. The underlying assumption made to allow the problem to be treated statistically is one of superposition, which does not exclude the ability to analyze nonlinear or time variant problems. This work initially describes the basic theory of statistical signal analysis, and the latest extensions to this theory which allow correlated jitter and data problems to be studied. Simple code implementation are given together with a real world example, to help the reader understand the mathematical analysis and its application. ]]> 32 2 260 267 618 While channel coding is a standard method of improving a system's energy efficiency in digital communications, its practice does not extend to high-speed links. Increasing demands in network speeds are placing a large burden on the energy efficiency of high-speed links and render the benefit of channel coding for these systems a timely subject. The low error rates of interest and the presence of residual intersymbol interference (ISI) caused by hardware constraints impede the analysis and simulation of coded high-speed links. Focusing on the residual ISI and combined noise as the dominant error mechanisms, this paper analyzes error correlation through concepts of error region, channel signature, and correlation distance. This framework provides a deeper insight into joint error behaviors in high-speed links, extends the range of statistical simulation for coded high-speed links, and provides a case against the use of biased Monte Carlo methods in this setting. Finally, based on a hardware test bed, the performance of standard binary forward error correction and error detection schemes is evaluated, from which recommendations on coding for high-speed links are derived. ]]> 32 2 268 279 1179 High-speed digital signal integrity at data rates above 6 Gb/s is an obstacle to reliable serial link operation. Two signal integrity challenges include dispersion due to frequency-dependent losses and reflections created at impedance mismatches. Signal integrity analysis relies on time-domain simulation of pseudo-random data patterns. This paper explores a predictive method for interconnect eye closure caused by reflections at the transmitter and receiver and does not require extensive time domain simulation. Worst-case bounds on intersymbol interference and data-dependent jitter aid prediction for link budgets under channel variations. This method is applied to the design of a passive equalizer. ]]> 32 2 280 289 984 The bandwidths of high-speed input/output (I/O) links keep increasing to meet the ever-growing demands for high-speed communications. The data rates for the leading edge high-speed I/O standards have already increased to around 10 Gb/s, including 10 GB Ethernet (GBE, 10 Gb/s, or 4 $,times,$10.3125 Gb/s, and 10$,times,$10.3125 Gb/s for Ethernet 40 G/100 G), 8$,times$ fibre channel (8.5 Gb/s), and PCI Express Gen 3 (at 8 Gb/s). At those data rates, the total available timing budget become less, data-dependent jitter gets severe, and jitter amplification becomes significant. This paper focuses on these jitter challenges and associated mitigation/reduction technologies, including jitter tracking via clock recovery, eye-opening via equalizations, and DCD cancellation via delay elements to avoid jitter amplification. ]]> 32 2 290 297 674 Frequency division multiple access is applied to bidirectional communication over chip-to-chip links. Frequency division is implemented by dividing the spectrum into low-frequency (dc) and high-frequency (ac) bands using a simple LC filter. The nonidealities that this filter introduces are compensated for with a transmitter/receiver pair that can recover signals in both bands. The receiver uses a dual-path topology that includes hysteresis to recover data from a signal with no dc content. The transmitter is a 6-tap (FIR) pre-emphasis equalizer with variable tap spacing. In simulation, the transmitter and receiver simultaneously communicate error-free at 8 Gb/s over the ac channel and at 500 Mb/s over the dc channel. Measurements shows that the ac and dc signals can be individually recovered and that the two signals occupy distinct frequency bands. ]]> 32 2 298 305 1843 As the input/output (I/O) data rate increases to several gigabits per second, determining the performance of high-speed interfaces using conventional simulation and measurement techniques is becoming very challenging. The models of the interconnects have to be broadband and accurate to represent high frequency and second-order effects such as frequency dependence of dielectric losses and surface roughness. The large and small signal behaviors of the transmitter and receiver circuitries have to be correctly represented in link analysis. In addition, the system simulation needs to properly capture the interactions between the circuits and interconnect subsystems to optimize the overall system. However, determining the values of the critical link parameters and their correlations can be complicated. Some of the key parameters are not deterministic and some cannot be observed directly. A combined modeling and measurement approach is indispensable to determine the performance of high-speed links. This paper presents the modeling and characterization techniques employed in the design and verification of a 16 Gb/s bidirectional asymmetrical memory interface. Direct frequency and time-domain methods as well as indirect techniques based on bit-error-rate testing are used to model and determine important link parameters. Complex de-embedding procedures are utilized to extract parameters from externally observed data. On-chip measurements are also used to complement off-chip instrumentation and accurately measure the true performance of the link. The modeling and characterization of prototypes are also discussed and model-to-hardware correlations are presented at component and system levels. Based on both simulation and measurement results, the behavioral model of the complete system is constructed and statistical simulation technique is used to predict the yield and performance at low bit error rate. ]]> 32 2 306 327 5053 What package improvements are required for dense, high-aggregate bandwidth buses running at data rates beyond 10 Gb/s per channel, and when might optical interconnects on the board be required? We present a study of distance and speed limits for electrical on-board module-to-module links with an eye to answering these questions. Hardware-validated models of advanced organic modules and printed circuit boards were used to explore these limits. Simulations of link performance performed with an internal link modeling tool allowed us to explore the effect of equalization and modulation formats at different data rates on link bit error rate and eye opening. Our link models have been validated with active, high-speed differential bus measurements utilizing a 16-channel link chip with programmable equalization and a per-channel data rate of up to 11 Gb/s. Electrical signaling limits were then determined by extrapolating these hardware-correlated models to higher speeds, and these limits were compared to the results of recent work on on-board optical interconnects. ]]> 32 2 328 344 4220 We have developed parallel optical interconnect technologies designed to support terabit/s-class chip-to-chip data transfer through polymer waveguides integrated in printed circuit boards (PCBs). The board-level links represent a highly integrated packaging approach based on a novel parallel optical module, or Optomodule, with 16 transmitter and 16 receiver channels. Optomodules with $16 ~{rm Tx}+ 16~{rm Rx}$ channels have been assembled and fully characterized, with transmitters operating at data rates up to 20 Gb/s for a $2 ^{7} -1$ PRBS pattern. Receivers characterized as fiber-coupled 16-channel transmitter-to-receiver links operated error-free up to 15 Gb/s, providing a 240 Gb/s aggregate bidirectional data rate. The low-profile Optomodule is directly surface mounted to a circuit board using convention ball grid array (BGA) solder process. Optical coupling to a dense array of polymer waveguides fabricated on the PCB is facilitated by turning mirrors and lens arrays integrated into the optical PCB. A complete optical link between two Optomodules interconnected through 32 polymer waveguides has been demonstrated with each unidirectional link operating at 10 Gb/s achieving a 160 Gb/s bidirectional data rate. The full module-to-module link provides the fastest, widest, and most integrated multimode optical bus demonstrated to date. ]]> 32 2 345 359 2164 32 2 360 361 205 In this paper, a novel transition design using vertical “coaxial transition” for coplanar waveguide (CPW-to-CPW) flip-chip interconnect is proposed and presented for the first time. The signal continuity is greatly improved since the coaxial-type transition provides more return current paths compared to the conventional transition in the flip-chip structure. The proposed coaxial transition structure shows a real coaxial property from the 3-D electromagnetic wave simulation results. The design rules for the coaxial transition are presented in detail with the key parameters of the coaxial transition structure discussed. For demonstration, the back-to-back flip-chip interconnect structures with the vertical coaxial transitions have been successfully fabricated and characterized. The demonstrated interconnect structure using the coaxial transition exhibits the return loss below 25 dB and the insertion loss within 0.4 dB from dc to 40 GHz. Furthermore, the measurement and simulation results show good agreement. The novel coaxial transition demonstrates excellent interconnect performance for flip-chip interconnects and shows great potential for flip-chip packaging applications at millimeter waves. ]]> 32 2 362 371 3333 Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using a surface mount compatible process. To demonstrate this concept, daisy chain test vehicles were fabricated on die measuring 11.5 mm $times$ 6.5 mm with 48 spring contacts on a 0.8 mm $times$ 0.65 mm grid array, each spring measuring 400 $, mu$m $times$ 100 $mu$m. The parts were placed onto organic boards with screen printed solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring using eutectic and lead-free solder. Assembled parts have undergone ${>}20thinspace 000$ hot plate thermal cycles and ${>}1000$ oven thermal cycles without failure. ]]> 32 2 372 378 2158 In this paper, a novel compliant chip-to-package interconnect, planar microspring, is presented in terms of design consideration, wafer-level fabrication process and mechanical characterization. Several spring designs have been evaluated, and results indicate that a $J$-shaped spring design produces a combination of high 3-D compliances and acceptable electrical parasitics. Further, numerical analyses on the $J$ -shaped microspring interconnect examined the dependence of mechanical and electrical performance upon geometry parameters. A wafer-level fabrication flow combining complementary metal oxide semiconductor (CMOS) back-end-of-line (BEOL) process and 3-D surface micromachining technique has been successfully implemented to create planar microspring interconnect prototypes with a fine pitch (100 $mu{rm m}$ ). The mechanical robustness of the prototype interconnects have been evaluated by nanoindentation. Finally, high-frequency electrical simulation suggested that the interconnect application can be extended up to $sim$35 GHz without significant power loss. ]]> 32 2 379 389 2828 In this study, a flexible wafer level packaging (FWLP) having the capability of redistributing the electrical circuit is proposed to resolve the problem of assembling a fine-pitched chip to a coarse-pitched substrate. In the FWLP, the diced chip is picked and back-sided attached to the flexible substrate after the functional testing. Besides, the solder on rubber (SOR) design is applied to expand the chip area and also to provide a buffer layer for the deformation energy from the coefficient of thermal expansion (CTE) mismatch. The design concepts as well as the fabrication processes for the fan-out type FWLP would be described herein. In our previous research, it was shown the reliability of FWLP could easily pass 1300 cycles thermal cycling test (JEDEC condition G, $-40^{circ}{rm C}sim 125^{circ}{rm C}$). Besides, the failure mode was moved from solders to copper trace lines. Therefore, the packaging level reliability of the copper trace structure of FWLP is investigated and discussed in this research. The $2^{5}$ factorial designs with the analysis of variance (ANOVA) are conducted to obtain the sensitivity information of the packaging. Through the reliability assessment and constrained optimization technology, the fan-out FWLP could be further improved within the target range of design parameters. The FWLP structure proposed in this research can be redesigned to have the double-sided I/O capability, and will have a high potential for various advanced packaging applications. ]]> 32 2 390 398 1503 32 2 399 401 678 This paper aims to demonstrate the utility of silicon interconnects for radio-frequency (RF) microelectromechanical system (MEMS) devices that are packaged using a wafer-scale encapsulation process. Design and fabrication steps for the packaged interconnects are described. Measurement results show that encapsulated devices can be operated at frequencies up to 6 GHz with less than 1 dB insertion loss from the through-package silicon interconnects. This paper also describes a simple and accurate lumped-element model for simulating the performance of packaged silicon interconnects. The model is verified with S-parameter measurements from 50 MHz to 6 GHz. The modeling method and extracted values are intended to aid in the design and simulation of RF MEMS devices packaged using this technology. ]]> 32 2 402 409 1543 In this paper, we address the often-neglected challenges of microfluidic packaging for biochemical sensors by proposing an efficient direct-write microfluidic packaging procedure. This low-cost procedure is performed through a programmable dispensing system right after a routine electronic packaging process. In order to prove the concept, the simulation, fabrication and chemical testing results of implemented hybrid system incorporating microelectronics and microfluidics are also presented and discussed. ]]> 32 2 410 416 1710 A miniaturized optical bioprobe package is developed using a 3-D micromirror and is tested for bio-imaging application. A silicon optical bench is designed and micromachined to assemble the fiber, lens, and the 3-D micromirror device. A 45$^circ$ angle trench is used to place the micromirror to achieve larger scanning range. Trace lines are formed on the optical bench and are connected to silicon micromirror using solder. A GRIN lens with lower numerical aperture has been used to focus the optical beam onto the micromirror. The bioprobe is packaged and is tested in a time domain optical coherence tomography (OCT) setup and optical image is obtained for plant tissue. ]]> 32 2 417 422 2074 Thermoelectric refrigerators (TEMs) offer several advantages over vapor-compression refrigerators. They are free of moving parts, acoustically silent, reliable, and lightweight. Their low efficiency and peak heat flux capabilities have precluded their use in more widespread applications. Optimization of thermoelectric pellet geometry can help, but past work in this area has neglected the impact of thermal and electrical contact resistances. The present work extends a previous 1-D TEM model to account for a thermal boundary resistance and is appropriate for the common situation where an air-cooled heat sink is attached to a TEM. The model also accounts for the impact of electrical contact resistance at the TEM interconnects. The pellet geometry is optimized with the target of either maximum performance or efficiency for an arbitrary value of thermal boundary resistance for varying values of the temperature difference across the unit, the pellet Seebeck coefficient, and the contact resistances. The model predicts that when the thermal contact conductance is decreased by a factor of ten, the peak heat removal capability is reduced by at least 10%. Furthermore, when the interconnect electrical resistance rises above a factor of ten larger than the pellet electrical resistance, the maximum heat removal capability for a given pellet height is reduced by at least 20% and the maximum coefficient of performance at low $K_{u-infty,u}/(NK)$ values is reduced by at least 50%. ]]> 32 2 423 430 1297 A design for cooling 3-D stacked chip electronics is proposed using solid heat spreaders of high thermal conductivity interleaved between the chip layers. The spreaders conduct heat to the base of an advanced synthetic jet cooled heat sink. The stack conduction was investigated parametrically through computational modeling. The effect of the power dissipated, the heat transfer coefficient applied to the peripheral surface, the spreader thickness, spreader thermal conductivity, and the shape of via holes in the spreader were modeled. Results show that for moderate power dissipations, 5 W in each 27 $,times,$38 mm layer, a 250 $mu$ m thick copper heat spreader would conduct heat adequately. In order to remove the heat from the edges of a five-layer stack and transfer it to the ambient air, a novel active heat sink design has been implemented using a matrix of integrated synthetic jets. In previous synthetic jet heat sink designs, cooling air is entrained upstream of the heat sink and is driven along the length of the fins, resulting in a significant rise in the air temperature and corresponding drop in streamwise heat transfer effectiveness. In the new design, synthetic jets emanate from the base of the fins so that the induced jets, and more importantly the entrained (cooling) ambient air, flow along the fin height. The significantly shorter flow path ensures rapid purging and replacement of the heated air with cool entrained air. Furthermore, in the matrix design the jets are spread uniformly throughout the heat sink such that all fin surfaces are subjected to the same airflow. The velocity field of the active heat sink is mapped using particle image velocimetry (PIV) and the configuration that maximizes the volume flow rate through the fins is investigated. Thermal performance is characterized using a surrogate heater and em- - bedded thermocouple sensors. The thermal performance of identical heat sinks cooled by the two synthetic jet approaches is compared. ]]> 32 2 431 439 926 We propose a method to quantify the true leak rate of micro to nano-liter packages using the helium mass spectrometer. A new concept called “preprocessing time” is introduced to take into account 1) the instability of the helium mass spectrometer during the initial part of its operation and 2) the contribution of viscous conduction to the total conduction. The proposed method utilizes the complete profile of the apparent leak rate measured by the mass spectrometer and determines the true leak rate by performing a nonlinear regression analysis. The method is implemented successfully to measure the true leak rate of micro-electro-mechanical system packages. The validity of the proposed scheme is corroborated experimentally. ]]> 32 2 440 447 1222 We have developed a novel all SU-8 packaging method for microelectromechanical system (MEMS) devices. The process is low temperature and low cost and it allows for nonhermetic as well as hermetic packaging. The nonhermetic package can be applied to sensors. The process flow is based on a partial and a full exposure of SU-8 negative resist using two masks. The underexposed region results in cross-linking of only a surface layer, while the underlying resist is not cross-linked and can be removed using SU-8 developer. By depositing a second SU-8 layer a sealed package for MEMS devices can be achieved. The packaging method provides any pattern and cavity clearance since it is solely based on lithography steps. The concept of the packaging method is introduced in this paper and then its practical validity demonstrated using simulation and characterization results. ]]> 32 2 448 452 1856 Cost effective microelectromechanical system (MEMS) packaging methods have been required, because the cost portion of the MEMS package is more than 80% of the manufacturing cost of a MEMS device. For this reason, cost-effective MEMS packaging is proposed in this paper for mass production using copper (Cu) lead frames (L/F) as a preplated frame (PPF). Package types include an epoxy molding compound (EMC) cavity wall and an on-frame type. The EMC-cavity package consists of a substrate, a cavity wall and a flat lid on top of the cavity. The on-frame package has a folded lid without a cavity wall. Finite element method (FEM) numerical modeling is performed to anticipate the mechanical warpage and stress of the packages. Assembled MEMS cavity packages were tested for wire pulling, lid pulling, hermetic test, and reliability tests in order to prove the feasibility of this packaging. The wire bonding strength was improved by 40% using plasma cleaning before wire bonding. Through a lid pulling test, a lid bonding strength of 2.40 kgf on average was obtained using an epoxy adhesive. Finally, all samples of the packages passed the reliability tests of the TC, HAST, and HTST, standardized by Joint Electron Device Engineering Council (JEDEC). Also, this cavity package showed excellent hermeticity through leak tests. ]]> 32 2 453 460 1080 The feasibility of ultrasonic bonding for hermetic microelectromechanical systems (MEMS) packaging has been demonstrated utilizing the solid phase vibration and welding process to bond two elements rapidly at low temperature. Two different approaches have been developed including lateral and vertical ultrasonic bonding setups with three sets of material bonding systems: In-to-Au, Al-to-Al, and plastics-to-plastics. The process utilizes purely mechanical vibration energy to enable low temperature bonding between similar or dissimilar materials without precleaning of the bonding surfaces. In these prototype demonstrations, the typical bonding process used tens of Watts at room temperature environment and the bonds were accomplished within seconds for bonding cavities with areas of a few mm$^{2}$ . Preliminary tests show that packaged MEMS cavities can survive gross leakage tests by immersing the bonded chip into liquids. As such, ultrasonic bonding could potentially be broadly applied for hermetic MEMS sealing and packaging especially where temperature limitation is a critical issue. Ultrasonic polymeric bonding could be applied for capping polymer-based microfluidic chips. This paper describes the ultrasonic bonding and hermetic sealing processes as well as the characterizations of bonding tools and equipment setups. ]]> 32 2 461 467 986 A new type of probe card is designed and fabricated for wafer-level integrated circuit (IC) testing. Using micromachining technology, roughly 18$thinspace$ 000 cantilever-tip probes can be integrated in one 4-in wafer, with a minimum pitch of 90 $mu$ m for adjacent probing tips. The probe card employs a silicon-and-metal composite structure, in which the bulk-micromachined silicon cantilever arrays provide uniform probing height and good planarity for the tips, as well as, the electroplated nickel probing tips feature high hardness and satisfactory electric contact with the pads to be tested. Electroplated nickel is used to simultaneously create the probing tips and the through-wafer interconnects (TWIs), which can transfer the testing signals from the dies-under-test (at the wafer bottom side) to the input/output (I/O) interface (on the front side). The probe card makes full use of the excellent mechanical properties of single-crystal silicon and satisfactory electrical properties of electroplated nickel, with the TWIs facilitating the following solder-bump flip-chip packaging. The fabricated cantilever-tip is able to withstand a contact force of 50 mN, corresponding to a tip displacement of 33 $mu$ m. The measured contact resistances on metal thin-film specimens (Al, Cu, and Au) are all below 1 $Omega$ , whereas the maximum current leakage across two adjacent tips is 90 pA at 5 V voltage. ]]> 32 2 468 477 4511 Electromigration (EM) and thermomigration (TM) are processes of mass transport which are critical reliability issue for next generation nanoelectronics. The purpose of this project is to study the influence of low temperature on EM and TM interaction. In this paper, a model for EM and TM process is proposed and has been implemented in finite element method. The governing equations include mass conservation, force equilibrium, heat transfer, and electricity conduction equations. A damage evolution model based on thermodynamics is introduced to evaluate the degradation in solder joints subjected to high current densities and high temperature gradients. The results are compared with experimental data to validate the model. ]]> 32 2 478 485 2351 A wafer-level vacuum package with getters deposited on the cap wafer is developed for an accelerometer device. An accelerometer wafer and cap wafer is bonded together in a vacuum of 1 mtorr and is characterized using a micro-electro-mechanical systems (MEMS) motion analyzer (MMA). Vacuum inside the package is measured indirectly by measuring the Q-factor response of the accelerometer structure inside the package. The obtained results indicated that there is variation from the center to the edge of the wafer. This may be due to difference in the outgassing of the package. Different reliability tests on the wafer-level package showed the package is robust to the reliability conditions. A progressive test on the Q-factor for different cycles of reliability test proved that there is no shift in the measurement value. A 3-D wafer-level package for accelerometer device is also developed to meet the requirements of vacuum packaging. Hermeticity and CV test showed no degradation in the device performance when subjected to reliability tests. ]]> 32 2 486 490 783 In this paper, we investigate fully embedded circular spiral inductors in multilayered organic packaging substrate for radio-frequency (RF) and microwave applications. The proposed spiral inductors are designed with circular geometry to improve their quality factors and the vertically stacked geometry is utilized to reduce the component area resulting in the increment of packaging density. And also the embedded circular spiral inductors are designed with conductor backed coplanar waveguide (CBCPW) structures for utilizing them directly for compact RF modules and systems. They are evaluated and optimized by varying their geometry parameters such as a number of turns, inner diameter, and embedded layer. These embedded inductors are accurately designed and analyzed by 3-D EM simulation and equivalent circuit modeling. The planar circular spiral two-turn inductor has inductance of 8.6 nH and maximum quality factor of 67 at 1 GHz. The vertically stacked circular spiral two-turn inductor has inductance of 10.2 nH and maximum quality factor of 66 at 1 GHz. The size of the vertically stacked inductor is approximately 70% of the planar one. The measured performance characteristics are well matched with the 3-D EM simulated ones. ]]> 32 2 491 496 995 Tungsten conductor lines deposited by focused ion beam (FIB) from W(CO)$_{6}$ precursor gas quite often have too high a resistivity (typically 100–200 $mu$ $Omega$ cm) in practical integrated circuit edit work. Even if the high resistivity of the deposited conductor line can be tolerated the FIB deposition process of conductor lines with length over 100 $mu$m can take several hours. This can cause serious problems in analogue or mixed signal type integrated circuit (IC) microsurgery often encountered in RF-band circuits. We present a method for the reduction of the FIB deposited tungsten conductor line resistance by subsequent laser chemical vapor deposition (LCVD) of copper from an organometal Cu(hfac)tmvs precursor. In this way, the resistance of the FIB deposited tungsten line can be reduced by order of magnitude from its original value by subsequent LCVD process. LCVD takes place selectively only on the FIB deposited tungsten line with high spatial resolution. As another practical application LCVD can be used to fabricate charge dissipation routes before FIB operations and thus protect transistors from charged ion beam induced discharge damages. Furthermore, the feasibility of the FIB/LCVD process in circuit edit work is discussed in this paper. Examples of both technologies used successfully in a combined way and the developed process flow for the circuit edit are presented. We applied the combined method to over different 200 circuit edit cases manufactured by various semiconductor processes. We found that the developed combined method could be used in about 20%–30% of the circuit edit cases to either improve the yield in circuit edit or speed up the total turnaround time. <- - /para>]]> 32 2 497 502 2964 This paper reports the development of thin film passive elements embedded within the interlayer of a silicon interposer. Thin film resistors were developed using a seed layer formed by the sputter semi-additive method. Inductor coils were designed as spiral coils, using Benzocyclobutene as the dielectric interlayer, and thin film metal–insulator–metal capacitors were formed using an anodizing tantalum oxide thin film as the dielectric layer and tantalum conductor films as capacitor electrodes. In this study, the fabrication process and the high-frequency properties of these passive elements are investigated. ]]> 32 2 503 508 2063 We report the development of a low cost, simple optical/electrical circuit board (OECB) using multimode polymer waveguide on FR4 printed circuit board (PCB). The design of this OECB uses only a 45 $^{circ}$-ended waveguide to couple and decouple the optical signal directly between the optical devices and the waveguide. The 45$^{circ}$ mirror is formed using excimer laser process on a multimode waveguide with temperature stability at reflow temperature. The optical waveguide is attached to a diced channel in the FR4 PCB using adhesive to form a completely planar circuit. This allows the laser diode and the photodiode to be assembled directly above the input and output of the waveguide using precision flip chip technology, which provides good alignment accuracy. This helps to increase the mechanical reliability of the circuit and minimize assembly requirements. Most importantly, all the electronic and optoelectronic devices used are commercially available components. In the paper, we report the details of the design, simulation result, and the testing results. ]]> 32 2 509 516 1225 The calculation of the threshold crossing time of the on-chip very large scale integration (VLSI) interconnects is an important part of interconnect simulation. The paper focuses on low-loss on-chip upper layer interconnect simulation. The work presents a new way of calculating the closed form output voltage and threshold crossing time formulas based on differential equation multiple scales solving method. The analytical form of output voltage for the step and ramp excitation is derived and the threshold crossing time formula is proposed. The presented approach of output voltage calculation for a single interconnect is extended to two coupled interconnects. ]]> 32 2 517 527 794 A disposable self-contained microfluidic package has been developed and tested for on-chip DNA extraction from human blood for practical lab-on-a-chip platform. The microfluidic package has been customized to allow easy interface between the microscale sample injection to the Si-based microscale sample preparation chip. For precise sample dispensing and to minimize dead volume and/or sample lost conical-shaped reservoirs have been employed. Reservoirs filled with reagents are sealed by a highly elastic thin rubber membrane. Automated actuation system has been designed and implemented for programmable sample/reagent dispensing using thin rubber membrane-plunger mechanism. The packaged DNA chip has been tested using blood sample and the testing protocol has been optimized to meet the requirements for DNA extraction. ]]> 32 2 528 535 2257 Half-sine acceleration-shock is prescribed to the supports of the printed circuit board (PCB) in the JEDEC JESD22-B111 test standard, which is used to evaluate the reliability of the board level solder joints to mechanical shock. In practice, it is near impossible to introduce an acceleration-shock of perfect half-sine and distorted excitations are common. This inconsistency is believed to be responsible for the poor reproducibility of the JEDEC test, yet there has been no serious attempt to investigate the effects of such distortion to the responses of the PCB. In this article, the distortion of the excitation was quantified and analytical solutions were developed for the distorted PCB responses by expressing the distorted excitation using Fourier series of odd function. The magnitude of distortion in the response of the PCB—measured by the percentage deviation in the amplitude of the distorted response from the ideal response—was found to be quantitatively equivalent to the magnitude of distortion in the half-sine excitation—measured by the percentage deviation in the enclosed area of the distorted excitation from the ideal half-sine excitation. Without proper control of the quality of the half-sine excitation, drop tests based on JEDEC JESD22-B111 performed at two different sites could produce PCB responses that are significantly different. To improve the reproducibility of the test, the surface strain on the PCB should be specified as the key test parameter, supplemented by the half-sine acceleration-shock of specified duration, leaving the amplitude adjustable to meet the desired surface strain on the PCB. ]]> 32 2 536 545 1115 Extensive understanding and management of the thermal–mechanical characteristics of novel packaging designs during the bonding process are indispensable to the realization of the technologies. Thus, this paper attempts to explore the bonding process-induced thermal–mechanical behaviors of an advanced flip chip (FC) electronic packaging. FC packaging employs a novel anisotropic conductive film, which is a thin composite film composed of polymer matrix and thousands of millions of highly oriented, 1-D silver (Ag) nanowires on the scale of 200 nanometers in diameter. For carrying out the process simulation, a process-dependent finite element (FE) simulation methodology that integrates both thermal and nonlinear contact FE analyses and a special meshing scheme is applied. The material properties of the nanoscale Ag wires are first explored using molecular dynamics (MD) simulations. By the characterized material properties of the Ag nanowires, the effective material properties of the composite film are derived through two theoretical approaches: 1) the rule-of-mixture (ROM) technique and 2) the proposed FE method-based approach. The predicted results by these two approaches are extensively compared with each other to examine the feasibility of using the widely used ROM technique for such cases. In addition, the validity of the proposed process-dependent FE simulation methodology is also confirmed through three experiments: 1) micro-thermocouple measurement of temperature; 2) Twyman-Green MoirÉ Interferometry measurement of out-of-plane deformations; and 3) Portable Engineering MoirÉ Interferometry measurement of in-plane deformations. Throughout the investigation, the effectiveness of the novel interconnect technology is demonstrated. Good agreement with the experiments is also obtained. It is found that the technology may ensure good electrical performance and structural integrity, not only at room temperature but even at elevated - - temperature, based on its substantial contact stresses but minor peeling stresses on the bonding line, together with a moderate, process-induced warpage on the substrate. ]]> 32 2 546 563 4014 This paper describes a detailed investigation of an ultrasonic nickel wire bonding technique for silicon carbide (SiC) devices, and its comparison with a thermosonic wire bonding process, for high-temperature applications. The study focuses on bonding 25-$mu{rm m}$-diameter Ni wires to 750-nm-thick Ni pads deposited on 3C-SiC substrates. First, the Ni wire bonding recipe is optimized for maximum bond strength using a response surface methodology (RSM) statistical approach. Maximum pull strengths as high as 13.1 gram force (gf) are achieved, far surpassing the military specifications for conventional Au (3.0 gf) and Al (2.5 gf) wire bonds. Scanning electron microscopy (SEM) and electron dispersive spectroscopy (EDS) are used to characterize crack defects on the heel of the bonded wires and verify the absence of cratering. Pull strength and electrical performance of the Ni wire bonds are studied up to 550 $^{circ}{rm C}$. The utility of Ni wire bonding to Ni pads for wire bonding prior to chemical release of SiC micromechanical devices in KOH and HF is demonstrated. Demonstration of use of Ni wire bonding with Ni pads in a SiC-based chemical sensor and a poly-SiC lateral resonant device is provided, up to 280 $^{circ}{rm C}$ operation for the former and 950 $^{circ}{rm C}$ the latter. Such devices are for example of interest in combustion-related sensor instrumentation. ]]> 32 2 564 574 3613 32 2 575 575 291 32 2 576 576 320 32 2 577 577 619 32 2 578 578 41 32 2 579 580 45 32 2 C3 C3 34 32 2 C4 C4 31