http://ieeexplore.ieee.org TOC Alert for Publication# 6040 2008 May 12 A complete and efficient transmission line simulation framework and the techniques involved are reported in this paper. A highly efficient finite-element quasi-TEM technique with comparable full-wave accuracy is applied as our fundamental simulation method. The fast quasi-TEM analysis is first performed over the entire frequency band with a self-estimation of solution accuracy. Then, depending on the requirement of accuracy, a switch frequency can be determined and a full-wave modal solver is automatically initiated to solve the problem up to the high frequency end. In addition, we apply improved model-order reduction methods in both the quasi-TEM and full-wave analyses to further speed up a simulation. Thus, the quasi-TEM and full-wave techniques as well as their associated model-order reduction methods are integrated to provide an efficient and accurate simulation from dc to very high frequencies. As for the versatility of the solver, the material loss, anisotropism, and frequency dependence are all taken into account in our formulations in order to provide a more complete field-based transmission line modeling. ]]> 31 2 326 338 1153 Two new 3-D chip stacking technologies, wire-on-bump (WOB) and bump-on-flex (BOF), are proposed and demonstrated with their prototypes. The WOB and BOF technologies are for low cost 3-D stacking of memory chips by vertical side interconnections with metal wires and flex-circuits, respectively. These new 3-D chip stacking technologies have benefits such as a shorter signal path and 3-D stackability of an unlimited number of chips compared to wire-bonded chip stacking. In the case of the BOF technology, additional active and passive components can be either surface-mounted onto or embedded into the flex-circuit, which is an added value that other chip stacking technologies have not demonstrated so far. More importantly, the WOB and BOF technologies enable lower cost processes than Si through-via technology, which is thus more suitable for memory chip stacking. This paper describes the detailed processes for our unique chip stacking structures with vertical interconnection methods of the WOB and BOF. Finite-element modeling and thermal cycle (TC) tests are also performed to address their thermo-mechanical reliability. ]]> 31 2 367 376 3839 In this paper, we study the characteristics of a novel miniaturized optical delay line, which delays light in a meandering photonic crystal waveguide, and describe the design steps. We show how lattice parameters and refractive index difference of the photonic crystal affect the bandgap width and suggest a criterion to select these parameters. Next, we focus on the parallel waveguide channels in photonic crystal, and analyze the impact of the channel length and the interchannel spacing on crosstalk. We suggest a method for mitering the sharp corners in meandering lines which reduces the undesired reflections by 8 dB. Considering all these guidelines, we examine the propagation of light in the proposed delay line through calculating time-delay and insertion loss. To achieve longer delays in a small device area, we concentrate on coupled cavities in photonic crystals and propose an approximate method for calculating the group velocity of light in the coupled defects. We show how by replacing waveguide channels of a meandering delay line with coupled defects we achieve time-delays more than 9 ps within a device size around 27 $mu$m, which corresponds to a miniaturization factor of 100. ]]> 31 2 311 319 1301 A novel “shunt attach” configuration for chip-scale thermoelectric (TE) generation of electric power from microprocessor waste heat is described, modeled, and parametrically analyzed. The generated electricity is used to drive a cooling fan that convectively cools the chip. A prototype using heat-driven cooling through off-the-shelf TE modules and a low-voltage fan was built and successfully applied to the thermal management of a high-power mobile processor in a portable equipment form factor. ]]> 31 2 429 437 953 The paper presents a generalized transmission line model able to describe the high-frequency mixed-mode propagation along electrical interconnects. The model is derived from a full-wave formulation and extends the validity of the standard transmission line (TL) model to frequency ranges where the propagation is no longer of transmission electron microscopy (TEM)-type. This generalized TL model describes the high-frequency differential and common mode propagation and the mode conversion. Within its validity limits, the proposed model provides solutions in good agreement with those obtained through full-wave models. Case studies are carried out to evaluate the high-frequency mode conversion in asymmetric interconnects. ]]> 31 2 275 284 653 TaNx thin films have attracted much attention for semiconductor integrated circuit (IC) packaging molding dies and forming tools due to their excellent hardness and thermal stability. Tantalum nitride (TaNx) thin films with TaN$_{0.63}$, TaN$_{1.14}$, TaN $_{1.58}$, TaN$_{2.19}$ , and TaN$_{2.81}$ were prepared using radio frequency (RF) sputter. The experimental results showed that the contact angle at 20 $^{circ}$ C go up with raising ${rm N}_{2}$ content to 119.2$^{circ}$ at beginning, corresponding to TaN $_{1.58}$, and then drop off. In addition, the contact angle components decreased with increasing surface temperature. Because increasing surface temperature disrupts the hydrogen bonds between water and the films and water vaporize gradually. The total surface free energy (SFE) at 20 $^{circ}$C decrease with ${rm N}_{2}$ content to raise to 39.6 mN/m(TaN$_{1.58}$) at the start, and then increase. A larger contact angle means a weaker hydrogen bonding, resulting in a lower SFE. The polar SFE component has same trend with total SFE, but the dispersive SFE component is on the contrary exactly. The polar SFE component is also lower than the dispersive SFE component. This results from hydrogen bonding being polar. The total SFE, dispersive SFE, and polar SFE of TaNx films decreased with increasing surface temperature. This is because water evaporation on the surface, disrupted hydrogen bonds, and surface entropy increase with increasing temperature. The film roughness has an obvious effect on the SFE and there is a tendency for the SFE to increase with increasing film surface roughness. SFE and surface roughness can be expressed as a function in direct ratio. ]]> 31 2 394 398 224 A common via filter is investigated and designed by using a proposed scalable lumped circuit model. The model-based result of the filter agrees well with that of the measurement. An ultra-compact open-ground spiral filter is proposed based on the common via filter. The open-ground spiral resonators are used to design second-order and fourth-order bandpass filters. The filter layouts, which affect filter performance in both passband and stopband, are investigated. The advantages of the open-ground spiral filter include not only its ultra-compact size (only $0.024lambda_{0}times 0.025lambda_{0}$) but also its additional transmission zero points and controllable stopband. ]]> 31 2 285 291 850 This paper reports major improvements to a 3-D full wave solver for a microstrip line and through-hole via in layered media. The interior layer problem, consisting of vias between two reference planes, is solved using the Foldy-Lax multiple scattering equations. The exterior layer problem is solved using the method of moments (MoM) with the layered media Green's functions. The exterior layer and interior layer problems are combined to obtain the S-parameters of the trace and through-hole via. A fast approach for calculating the layered-medium Green's functions using the numerical modified steepest descent path method is utilized. The Green's functions require milliseconds to compute per point. Schemes for efficiently computing image contributions for the static portion of the mixed potential Green's function are also implemented to solve the neighboring or self-RWG (basis function) interaction in the MoM problem. To validate the accuracy of the solution, extensive comparison with Ansoft's HFSS versions 9 and 11 for different pad sizes and antipad sizes are presented. The CPU per frequency is also tabulated to demonstrate the speed of the approach in this paper. ]]> 31 2 292 302 1461 A new method to reduce the computation time in power/ground-plane analysis is proposed. The proposed method is based on an approximation of impedance in the frequency domain using Mobius transform. The power/ground plane impedance is transformed by Mobius transform and is more linear than the raw impedance, which ensures that a simple approximation is possible. After the approximation, an inverse Mobius transform is applied to predict the power/ground plane impedance. This method displays the high speed of computing with good accuracy. In the case of impedance calculation for a 17.78 cm $,times,$10.16 cm printed circuit board (PCB) board, the proposed method has shown to be 12 times faster than conventional methods. This method can be applied to the analysis and design of power/ground-plane where complex computation is needed. ]]> 31 2 320 325 560 The aim of this study is to characterize the behaviors of laser-welded joint between pure nickel (Ni200) weld clip and Kovar base metal under various mechanical loadings, i.e. shear and fatigue in shear. A Nd:YAG laser source with 1064 nm was used to weld a $1.0times 1.0times 0.2 {rm mm}$ Ni200 piece onto a Kovar substrate by single weld spot. These samples were then subjected to shear test. While the shear fatigue cyclic tests on the four welding spots that joined Ni200 saddle shape weld clip onto the Kovar base metal. Results show that power density is the key parameter that determines the beam penetration depth and overlapping area. The pulse width has dominant effects on the weld width while the charge voltage dominant the depth of penetration and thus increases the absorbed power density. The maximum shear force requires to break a joint is ranged between 90¿95, 70¿75, and less than 45 N when welded by 380, 360, and 340 V, respectively. The shear strength is very much depends on the spot welding diameter and beam penetration depth. In general, higher pulse width increases the joint diameter and thus reduces the shear strength. The condition of dimples observed in the fracture surface after shear test provides important indication on the properties of the weld joints. The fatigue life for the weld formed by using the selected welding condition ranges from 1178 to 1813 cycles. The fatigue ratios obtained show that the stress below endurance limit has about 17%¿23% possibility that fatigue failure will never occur for joints formed by using this range of welding conditions. The surface condition of the fracture surface after shear fatigue test provide direct indication on the crack propagation rate. Observations of all fracture surfaces by scanning electron microscope (SEM) help in understanding the deformation and damage mechanisms of Ni200 laser-welded joint at room temperature. ]]> 31 2 386 393 5259 An efficient Delaunay–Voronoi modeling of the power-ground planes suitable directly for SPICE compatibity is proposed to deal with the ground bounce noise and decoupling capacitors placement problems for the high-speed digital system designs. The model consists of virtual ports and triangular meshes with the lumped circuit elements, in which all the element values can be related to the mesh geometry shape by the analogy between the circuit equations and Maxwell's equations. Since the analogy fails to apply due to the singular fields near the input/output pins, the via effect of driving and sensing ports is not negligible and an analytical expression from the Hankel function is thus presented for the correction term. A simple rule has been investigated for the model with minimum lumped circuit elements to accurately represent the power-ground planes over the frequency range of interests. The full-wave simulation and measurement results verify the good correlations with the proposed models for the impedance responses of regular and defective plane shapes. ]]> 31 2 303 310 1345 Polymer optical waveguides are viewed as a potential interconnect solution in board-level optoelectronic systems. In this paper, the optical loss changes in siloxane polymer waveguides during thermal aging conditions are studied for the wavelengths of 850 and 1310 nm. The optical loss in waveguides during intended operation and temperature exposure can increase due to factors such as oxidation of waveguides, increased absorption, and scattering. In addition to these inherent changes in the optical properties of the waveguides, physical failures such as delamination and cracking of waveguides will also increase the optical loss. This paper focuses on the first set of parameters that affects the optical loss and as a first step; the optical absorption of the polymer material is characterized through spectroscopy experiments. The thermal-aging dependent optical loss is determined for waveguide samples at several different accelerated temperature conditions. The temperature contours in a polymer waveguide with an embedded laser are determined from experiments as well as finite-element modeling. Using experimental data, analytical models have been developed that relate the optical loss with temperature and time, and provide a practical way of determining the reliability of the optical waveguides during field-use conditions. ]]> 31 2 410 416 791 We demonstrate a micromachined flexible chip-to-board chip interconnect structure for a chip scale package. Micromachined flexible interconnects enable robust operation in high thermal cycling environments, even for high pinout chips due to the flexible interconnect ability to absorb thermal expansion strain. The interconnects on the chip-side and printed wiring board (PWB)-side are united by electroplating bonding technology, a direct bonding technology resulting in solder-free, underfill-free, low temperature joining by means of copper (Cu) electroplating. Over 200 surface micromachined interconnects, which have a thermal relief geometry, are radially arranged on 1 $,times,$1 cm$^{2}$ substrates. A chip surrogate consisting of glass with integrated platinum (Pt) microheaters mimics a real electronic device under varying thermal loads. The integrated microheaters can simultaneously test mechanical and electrical performance of the interconnects by generation of on-chip temperatures up to 150 $^{circ}$ C . Lateral and vertical displacement of the interconnects in the thermal environment are measured and simulated. A mechanical reliability test of the chip scale package is successfully performed for 5000 cycles with thermal cycles of 5 min between 40 $^{circ}$C to 147 $^{circ}$C . No failures were observed during this period. ]]> 31 2 357 366 1449 The complicated geometry of high-density interconnect structures in multilayer, planar substrates is one of the major hurdles in the application of finite element methods for their multigigahertz electromagnetic analysis. In addition to compounding the complexity in the generation of the finite element grid, the multilayer nature of the structures and their multiscale attributes result in finite element systems of very large dimension which, more often than not, are not well conditioned. This paper presents a domain decomposition methodology for overcoming these hurdles. More specifically, the proposed methodology utilizes the multiple power and ground planes used in such structures as natural physical boundaries for their decomposition into a set of subdomains, each one of which is meshed and discretized separately from the rest. The electromagnetic interaction between the domains is effected through the enforcement of tangential field continuity conditions at the voids and via holes present at the power and ground planes. In particular, a Krylov subspace model order reduction approach is used to facilitate the broadband solution of the multilayer interconnect structure. The proposed modeling methodology is demonstrated through its application to the electromagnetic analysis of several multilayer interconnect structures. ]]> 31 2 339 350 1461 The 1.3/1.55-$mu{hbox{m}}$ bidirectional small form pluggable (SFP) optical transceiver with an integrated wavelength division multiplexing (WDM) subassembly using accurate ceramic blocks has been developed. The WDM subassembly on which a laser diode, a receiver photodiode, a WDM filter, and two microlenses are integrated is only ${hbox{2.0}}times {hbox{2.1}}times {hbox{0.6}} {hbox{mm}}^{3}$ in size and inserted in a TO-CAN package. The SFP transceiver coupled with single-mode fiber has been operated at a 622-mb/s data rate. The transmitted optical output power is $-$2.8 dBm and the measured value of sensitivity is $-$32 dBm at 10$^{-10}$ bit-error rate. ]]> 31 2 423 428 1883 The performance of current high-speed consumer electronic systems is often compromised by degradation caused by distortion in eye patterns. This paper proposes a systematic method that uses the voltage transfer function for arbitrary source and load terminations to improve the eye patterns of high-speed differential links with passive components that minimize distortion. This approach is cost-effective since it only utilizes commercially available surface-mount components. The methodology has been validated by measurements in this paper. ]]> 31 2 246 257 2398 The performance of embedded planar capacitors in noise suppression of input/output (I/O) circuits and improvements in board impedance profile have been investigated in this paper. Simultaneous switching noise (SSN) is a critical issue in today's systems and this paper shows performance improvements by introducing thin planar embedded capacitors in the board stack up. Measurement and modeling results by including the effects of transmission lines and the power ground plane pairs in the board stack up in the gigahertz range quantify the performance of the embedded capacitors. ]]> 31 2 234 245 2227 We have developed 40-Gb/s traveling-wave electroabsorption-modulator-integrated distributed feedback laser (TW-EML) modules using several advanced technologies. First, we have adopted a selective area growth (SAG) method in the fabrication of the 40-Gb/s EML device to provide active layers for the laser and the electroabsorption modulators (EAMs) simultaneously. The fabricated device shows that the measured 3-dB bandwidth of electrical-to-optical (E/O) response reaches about 45 GHz and the return loss $({ S}_{11})$ is kept below $-$10 dB up to 50 GHz . For the module design of the device, we mainly considered electrical and optical factors. The measured ${rm S}_{11}$ of the fabricated 40 Gb/s TW-EML module is below $-$ 10 dB up to about 30 GHz and the 3-dB bandwidth of the E/O response reaches over 35 GHz. We also have developed two types of coplanar waveguide (CPW) for the application of the driver amplifier integrated 40 Gb/s TW-EML module, which is a system-on-package (SoP) composed of an EML device and a driver amplifier device in a module. The measured ${ S}_{11}$ of the two-step-bent CPW is below $-$10 dB up to 35 GHz and the measured ${ S}_{11}$ of the parallel type CPW is below $-$10 dB up to 39 GHz. ]]> 31 2 351 356 1444 A new type of composite filler mechanically treated with multi-walled carbon nanotubes (MWNTs) and ${hbox{BaTiO}}_{3}$ (BT) particles was prepared to produce higher dielectric properties in the composite. The hybrid film fabricated by incorporating these composite fillers in an epoxy matrix had a high dielectric constant and similar dielectric loss as compared to the composite which contained neat BT particles. The dielectric properties of these hybrid films were found to be dependent on both the content of MWNTs and mechanical processing time. Results suggest that this novel hybrid film composed of the composite filler and the epoxy matrix can be used for embedded capacitor material. ]]> 31 2 417 422 2406 A 40-Gb/s packaging solution that uses low-cost wire-bonded plastic ball grid array (WB-PBGA) technology is presented. Since such a high speed was beyond the reach of conventional package designs, a new design methodology was proposed—discontinuity cancellation in both signal-current and return-current paths. The 3-D structures of bonding wires, vias, solder ball pads, and power distribution networks were optimized for the discontinuity cancellation. Two versions of four-layer WB-PBGA packages were designed; one according to the proposed methodology and the other conventionally. The proposed design methodology was verified with full-wave simulation, passive bandwidth measurement, time domain reflectometry (TDR), eye diagram measurement, and jitter analysis. ]]> 31 2 258 266 1993 This paper demonstrates a flux/2-ethyl-1-hexanol mixture capable of performing a self-assembly process. An ${rm O}_{2}$/Ar plasma treatment controls the surface free energy of Si, leading to better self-assembly driven by capillary force. Hydrophobic bonding pads resulting from ODT (1-octadecanethiol) SAMs (self-assembled monolayers) on a microchip can be self-assembled on hydrophobic bonding sites caused by a flux/2-ethyl-1-hexanol mixture on a substrate within 0.4 s. Microchips with 400$,times,$200 $mu {rm m} ^{2}$-rectangle bonding pads exhibited higher alignment precision (displacement error $=13.2~mu {rm m}$; rotation error $=3.3^{circ}$) than 400 $,times,$400 $mu {rm m} ^{2}$-squares. The Owens-Wendt method was used to calculate the contact angle of 2-ethyl-1-hexanol to different bonding surfaces in water. Plasma treatment enabled the smallest contact angle of 2-ethyl-1-hexanol to ODT-modified Au surface (4.4$^{circ}$ ), and the largest contact angle of 2-ethyl-1-hexanol to plasma-modified Si surface (153.5$^{circ}$) in water. It explained why the plasma treatment exhibited benefit of self-assembly. This self-assembly technique could be used to assemble light emitting diodes, RFID tags, biosensors, or other types of microchips. ]]> 31 2 404 409 1159 31 2 C1 233 68 31 2 C2 C2 39 31 2 C3 C3 33 31 2 C4 C4 32 This paper presents a feasibility study of using eddy current induced heating for the solder reflow of area array packages. With a high frequency electromagnetic field, Sn3.5%Ag lead-free solder balls were heated to melt and wet the solder pads on an organic substrate. The experimental results showed that such a solder reflow process could be implemented effectively in a wide processing window. With an infrared temperature sensor, it was found that the temperature difference between the solder balls and the FR4 board might reach 80 $^{circ}{rm C}$ , indicating a rather localized heating mechanism. In addition, the heating and cooling rates during the soldering were found very high. This is another feature of the induction heating reflow process. It was also found that the generated temperature in the solder balls would depend on the size of the solder balls. This characteristic may be used to perform selective soldering of flip chip BGA packages. Furthermore, the developed soldering process was applied to the board level reflow of actual components. The result verified that the induction heating reflow is a feasible soldering process in actual applications. ]]> 31 2 399 403 969 This paper presents a semi-analytical approach for electrical performance modeling of complex electronic packages with multiple power/ground planes and large number of vias. The method is based on the modal expansion technique and the method of moments. For the inner package domain with multiple power/ground planes and many vias, the modal expansion method is employed to compute the electromagnetic fields from which the multiport network parameters, e.g., the admittance matrix can be easily obtained. For the top/bottom domain of signal layers, the moment method is used to extract the equivalent resistance, inductance, capacitance, and conductance (RLCG) parameters. The equivalent circuit for the entire package is then generated by combining the results for both package domains. The equivalent circuit can be used in a SPICE-like simulator to study the signal and power integrity of an electronic package. Numerical examples demonstrate that the new approach is able to provide fast yet accurate signal and power integrity analysis of multilayered electronic packages. ]]> 31 2 267 274 1073 A wafer level packaging technique has been developed with an inherent advantage of good solder joint co-planarity suitable for wafer level testing. A suitable weak metallization scheme has also been established for the detachment process. During the fabrication process, the compliancy of the solder joint is enhanced through stretching to achieve a small shape factor. Thermal cycling reliability of these hourglass-shaped, stretch solder interconnections has been found to be considerably better than that of the conventional spherical-shaped solder bumps. ]]> 31 2 377 385 2969 31 2 438 439 45 31 2 440 440 41