http://ieeexplore.ieee.org TOC Alert for Publication# 6040 2009 November 06 32 4 C1 C1 48 32 4 C2 C2 40 32 4 709 710 24 Thermomechanical reliability of solder joints in flip-chip packages is usually analyzed by assuming a homogeneous underfill ignoring the settling of filler particles. However, filler settling does impact flip chip reliability. This paper reports a numerical study of the influence of filler settling on the fatigue estimation of flip-chip solder joints. In total, nine underfill materials ( 35 vol% silica filler in three epoxies with three filler settling profiles for each epoxy) are individually introduced in a 2-D finite element (FE) model to compare the thermal response of flip chip solder joints that are surrounded by the underfill. The results show that the fatigue indicators for the solder joints (inelastic shear strain increments and inelastic shear strain energy density) corresponding to a gradual, nonuniform filler profile studied in this paper can be smaller than those associated with the uniform filler profile, suggesting that certain gradual filler settling profiles in conjunction with certain resin grades may favor a longer solder fatigue lifetime. The origin of this intriguing observation is in the fact that the solder fatigue indicators are a function of the thermal mismatch among the die, substrate, solder, and underfill materials. The thermal mechanics interplayed among these materials along with a gradual filler profile may allow for minimizing thermal mismatch; and thus lead to lower fatigue indicators. ]]> 32 4 711 719 985 Most TSVs are filled with copper; siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (${sim} 17.5 times 10^{-6}/^{circ}$ C) is a few times higher than that of silicon ( ${sim}2.5 times 10^{- 6}/^{circ}$C). Thus, when the copper filled through silicon via (TSV) is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the copper and the silicon/dielectric (e.g., SiO$_{2}$), which will create very large stresses and strains at the interfaces between the copper and the silicon and between the copper and the dielectric. These stresses/strains can be high enough to introduce delamination between the interfaces. In this paper, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter). One of the major applications of TSV is as an interposer. Because of Moore's (scaling/integration) law, the silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional substrates, e.g., BT (bismaleimide triazine) cannot support these kinds of silicon chips anymore and a silicon interposer (substrate) is needed to redistribute the very fine-pitch and high pin-count pads on the chip to much larger pitch and less pin-count through the silicon vias on the silicon substrate. Depending on the via-size and pitch of the copper filled TSV, the effective CTE of the copper filled TSV interposer could be as high as $10 times 10^{- 6} /^{circ}$C. Consequently, the global thermal expansion mismatch between the silicon chip and the copper filled TSV substrate can be very large and the bumps (usually very small, e.g., microbumps) between them may not be able to survive under thermal conditions. In this study, the nonlinear stresses and strains in the microbumps between the silicon chip and copper filled TSV interposer (with and without underfills) have been determined for a wide-range of via sizes and pitches, and various temperature conditions. These results should be useful for 1) making a decision if underfill is necessary for the reliability of microbumps and 2) selecting underfill materials to minimize the stresses and strains in the microbumps. ]]> 32 4 720 728 1990 Current techniques for nondestructive quality evaluation of solder bumps in electronic packages are either incapable of detecting solder bump cracks, or unsuitable for in-line inspection due to high cost and low throughput. As an alternative, a solder bump inspection system is being developed at Georgia Institute of Technology using laser ultrasound and interferometric techniques . This system uses a pulsed Nd:YAG laser to induce ultrasound in electronic packages in the thermoelastic regime; it then measures the transient out-of-plane displacement responses on the package surfaces using laser interferometric technique. The quality of solder bumps in electronic packages is evaluated by analyzing the transient responses. This paper presents a systematic study on thermomechanical reliability of flip chip solder bumps using laser ultrasound–interferometric inspection technique and finite element (FE) method. The correlation between the failure parameter extracted from FE simulation for evaluating solder bump reliability and quality degradation characterization of solder bumps through noncontact, nondestructive laser ultrasound testing has also been investigated. ]]> 32 4 729 739 1886 The current trend in the electronics industry is to decrease the size of electronic components while attempting to increase processing power and performance. This is leading to increased interest in thinner printed wiring boards and finer line width and pitch. However, these goals can be hindered by the occurrence of warpage in the manufacturing and assembly process of electronic packages from mismatches in thermomechanical properties of the materials used. Warpage can be problematic as it leads to misalignments during package assembly, reduced tolerances, and a variety of operational failures. Current warpage prediction techniques typically utilize volume averaging to estimate material properties in layers of copper mixed with interlayer dielectric material. These techniques use copper percentages for an entire layer and do not account for trace orientation. This paper describes the development of a new methodology to predict the warpage of a particular substrate. The developed methodology accounts for both the trace pattern planar density and planar orientation in material property calculations for each layer of a multilayer substrate. This process has been used to calculate the warpage of actual substrates and the results of using the developed methodology are shown to agree well with experimental data. ]]> 32 4 740 745 1346 One approach to 3D technology is chip stacking using through-silicon vias (TSVs). Interconnects in a 3D assembly are potentially much shorter than in a 2D configuration, allowing for faster system speed and lower power consumption. However, it is extremely important to use cost-effective process technologies in practical use. Therefore, in our study, we propose a basic concept for interconnecting stacked chips with TSVs using a cost-effective process technology. The principal feature is to use a “mechanical-caulking” technique, which has been used widely in the mechanical-engineering field, enabling 3D interconnections between stacked chips. This makes it possible to interconnect them by only applying compressive force at room temperature. This paper presents the results obtained by using mechanical-caulking connections at room temperature accomplished by manufacturing a prototype of a chip-stacked package with TSV interconnections. A 3D-SiP composed of an existing MCU, an interposer, and an SDRAM chip with TSV interconnections was also manufactured. However, a customized design, assuming TSV interconnections in the existing MCU, needs to be introduced for practical use to achieve ${rm SiO}_{2}$ etching with shorter turn around time (TATs) and high TSV yields of more than 99%. ]]> 32 4 746 753 2661 Elastic properties of a solid are closely related to many fundamental solid-state properties. Theoretical calculations on elastic constants are well motivated by the advance in computational technologies, especially when mechanical testing on submicron components is extremely difficult. Elastic constants of a number of anisotropic lattice systems have been calculated based on the density functional theory, and good agreements between computational and experimental results have been found. In this study, we report elastic properties of the Cu-Sn crystalline phases, the $varepsilon$-Cu $_{3}$Sn and $eta$-Cu $_{6}$Sn $_{5}$, using first-principles calculations. The polycrystalline moduli obtained using the Voigt-Reuss scheme are 134.16 GPa for Cu$_{3}$ Sn and 125.98 GPa for Cu$_{6}$ Sn$_{5}$ . Calculation results show that these Cu-Sn crystalline phases have the greatest stiffness along the $c$ -direction. In particular, the results reveal the unique anisotropic feature along $a$ - and $b$ -directions within the Cu$_{3}$ Sn superstructure, which can hardly be resolved from experiments. Our results also suggest that the most compliant stiffness in the long-period direction is assoc- iated with the lattice modulation within the Cu$_{3}$Sn superstructure. ]]> 32 4 754 757 599 The adhesion between electrolessly deposited copper and an epoxy-containing dielectric material has been investigated. In particular, the role of mechanical anchoring and chemical bonding in these systems has been examined. The contribution of each of these mechanisms to adhesion has been identified. Probelec, a phenolic-novolac epoxy polymer, and Avatrel, an addition polymerized norbornene polymer with an epoxy side-group, have been tested in this study. Traditional swell and etch treatments have been used to enhance mechanical anchoring through pore-type roughness development on the phenol-novolac epoxy, but were found to be ineffective in roughening the Avatrel surface. The critical difference between the two polymers is the epoxy-backbone (for the phenolic epoxy) versus the epoxy side-group (for the norbornene backbone polymer). In order to create roughness on the Avatrel surface, a novel technique utilizing a blend of Avatrel and Probelec was investigated. This technique created pore-type roughness and enhanced mechanical anchoring on the Avatrel surface. ${rm NH}_{3}$ plasma treatments were utilized to enhance the chemical bonding contribution to adhesion and produce surfaces with peel strengths of 0.15–0.25 N/mm with minimal roughness generation. Finally, a combined wet-chemical and plasma treatment protocol was investigated to enhance chemical bonding and mechanical anchoring on the same surface. Samples with adhesion greater than 0.5 N/mm with roughness less than 50 nm were produced with both Avatrel and Probelec. Through the use of a combined wet-chemical and plasma-surface treatment the polymer surface has been optimized for adhesion while minimizing roughness. ]]> 32 4 758 767 3019 Thermal stress, which is caused by the difference in thermal expansion coefficients of different materials, is a serious problem for large scale integrated (LSI) circuit packaging. The stress causes damage to LSI devices, especially those that have low-k materials in their LSI layer, and packaging substrates. We have developed a helical-micro-spring (HMS) to reduce damage due to thermal stress. The spring has a helical wiring structure that relieves any thermal stress. We have fabricated the HMS using a negative-type photopolymers or a positive-type photopolymer as dielectric layers. We have also simulated the spring's mechanical and electrical properties and compared the properties with other stress relaxation structure. ]]> 32 4 768 772 860 A novel three-dimensional packaging method for Al-metalized SiC power devices has been developed by means of Au stud bumping technology and a subsequent vacuum reflow soldering process with Au-20Sn solder paste. Al-metalized electrodes of a SiC power chip can be robustly assembled to a direct bonded copper (DBC) substrate with this method. The bump shear strength of a Au stud bump on an Al electrode of a SiC chip increased with bonding temperature. The die shear strength of a SiC chip on the DBC substrate increased with the number of Au stud bumps which were preformed on the Al electrode. The bonded SiC-SBD chips on a DBC substrate were aged at 250 ${^circ}{rm C}$ in a vacuum furnace and the morphologies, die shear strength and electrical properties were investigated after a certain aging time. After 1000 h aging at 250 ${^circ}{rm C}$, the electrical resistance of the bonded SiC-SBD chips only increased about 0.4%, the residual die shear strength was much higher than that of the IEC749 (or JEITA) standard value, and little morphological change was observed by a micro-focus X-ray TV system. Very little diffusion between Au stud bumps and Au-20Sn solder was observed by scanning electron microscope (SEM) equipped with an energy dispersed X-ray analyzer (EDX). Intermetallic compounds (IMC) evolved at the interface of chip/solder and chip/Au stud bumps after 1000 h aging at 250 ${^circ}{rm C}$. With this method, power devices with Al bond pads can be three-dimensionally packaged. ]]> 32 4 773 779 2370 We have designed and fabricated both single-coil and parallel-coil magnetic integrated inductors with extremely small resistances and high quality factors on an 8-in-round printed circuit board (PCB) substrate for microprocessor power delivery applications. The dc resistances of these inductors are less than 12 ${hbox{m}} Omega $. Soft magnetic material CoFeHfO was successfully integrated into the inductor fabrication to increase the inductance. The quality factors are more than 80 in a frequency range of 1.5–2 GHz for air-core inductors and more than 23 in a range of 200–300 MHz for magnetic inductors. The net inductance improvement of the magnetic inductor over air-core inductor is about 12%, which could be further enhanced with a thicker magnetic core, according to our theoretic calculation and HFSS simulation. We also characterized the permeability spectra of CoFeHfO material on the PCB substrate, simulated the high-frequency performance of the magnetic integrated inductor by HFSS, and, for the first time, reached a good agreement with the experimental data. The experimental and simulation results of the magnetic inductors as compared to those of the air-core inductors point out the future direction to further optimize magnetic integrated inductors. ]]> 32 4 780 787 1315 A locally matched flip-chip (LMFC) interconnect that uses a capacitive compensation technique to minimize impedance mismatch in coplanar waveguide lines is described. With an optimum percentage change in capacitance of 55$, pm ,$5%, we observe return loss below 25 dB over 90% of a 50 GHz bandwidth. When compared to a conventional flip-chip method, the minimum performance improvement in return loss is 10 dB and the insertion loss is smooth up to 30 GHz. The LMFC interconnect consists of two micromachined features: 1) an air cavity underneath the chip and 2) local trenches in the transition region of the flip-chip interconnect interface. A comparison of different LMFC interconnect designs to the conventional flip-chip approach is made, and design rules to obtain local trench dimensions are discussed. ]]> 32 4 788 796 1107 Recent developments in liquid crystalline polymer (LCP)-based processing technology have shown that highly-integrated, fully-packaged radio-frequency (RF) front-end modules with high-performance can be designed by using the system-on-package (SOP) approach. However, the direct integration of a large antenna element to a small module package still remains an issue. This paper presents a novel conformal antenna structure, which results in a compact integration of the antenna and the module package for 5 GHz WLAN/WiMAX applications. The extension of 5 GHz single-band operation to 2.4/5 GHz dual-band operation is also discussed in this paper. The antenna is an inverse L-shaped monopole printed on a 25-$mu{hbox {m}}$-thick flexible LCP layer, which protrudes from a rigid multilayer organic substrate. The shielding effects of a grounded metal case, which can house the associated module circuitry, are also considered during the design process. The metal case serves as a vertical ground plane for the antenna in addition to protecting the module circuitry from the near-fields of the antenna. The flexible LCP substrate can be bent and folded over the module case, resulting in a compact design and the tight integration of the antenna with the front-end module. The details of the design and the fabrication of the proposed structure as well as the simulation and the measurement data are presented in this paper. ]]> 32 4 797 808 2521 Optimization of radio-frequency identification (RFID) tags often requires several iterations of antenna design/fabrication/testing to meet cost and performance targets. The use of a rapid prototyping approach for antenna development would allow the designer an inexpensive and fast route to the refinement process. In this study, the performance of a commercial-off-the-shelf ultrahigh frequency (UHF) etched copper antenna was compared to printed silver antennas prepared by the following three direct-write techniques: maskless mesoscale materials deposition; matrix-assisted pulsed laser evaporation direct-write; and, collimated aerosol beam direct-write. The morphologies of the antennas were analyzed using contact and optical profilers with sheet resistance also being measured. Operational characteristics were determined by mounting silicon integrated circuits (IC) to the four different types of antennas. The performance of tags that utilized direct-write silver antennas was comparable to the copper-based commercial tag. To our knowledge, this is the first demonstration where some of the direct-write rapid prototyping attributes (e.g., slight overspray, overlap of written lines, overall thickness less than 500 nm) are shown to not seriously impede RFID tag performance. These results demonstrate the utility of direct-write for rapid prototyping studies for UHF RFID antennas. ]]> 32 4 809 815 734 Transient simulation using Laguerre polynomials is unconditionally stable and is ideally suited for modeling structures containing both small and large feature sizes. The focus of this paper is on the automation of this technique and its application to chip-package cosimulation. Laguerre finite-difference time-domain (FDTD) requires using the right number of basis coefficients to generate accurate time-domain waveforms. A method for generating the optimal number of basis functions is presented in this paper. Equivalent circuit models of the FDTD grid have been developed. In addition, a method for simulation over a long time period is also presented that enables the extraction of the frequency response both at low and high frequencies. A node numbering scheme in the circuit model of the FDTD grid that is suitable for implementation has been discussed. Results from a chip-package example that shows the scalability of this technique to solve multiscale problems have been presented. ]]> 32 4 816 830 2159 The inability to accurately determine the die level current draw of microprocessors is a significant gap in the analysis and design of microprocessor power delivery networks (PDNs). Although low frequency methods of direct measurement are available, the large number of power and ground connections on a package makes high frequency measurements extremely difficult. This paper successfully demonstrates that the instantaneous load current can be accurately estimated to over 500 MHz with only a wide bandwidth measurement of the voltage at the die. The current estimate is obtained by using the measured output impedance to create a band-limited inverse filter to solve the linear deconvolution problem. The accuracy of the algorithm is verified by correctly estimating known loads drawn by a functioning microprocessor. Two separate methods are then used to estimate the instantaneous load current of a microprocessor executing instructions, and wide bandwidth ${rm i}_{rm o} ({rm t})$ results are presented and discussed. ]]> 32 4 831 840 912 32 4 841 841 43 32 4 842 843 46 32 4 844 844 629 32 4 845 845 205 32 4 846 864 178 32 4 C3 C3 34 32 4 C4 C4 31