Advanced Packaging, IEEE Transactions on - new TOC

Nov. 2010

IEEE Transactions on Advanced Packaging publication information

Nov. 2010

Editorial CPMT Society to Merge Transactions in 2011

Nov. 2010

Our Thanks to Reviewers IEEE Transactions on Advanced Packaging

Nov. 2010

Foreword Special Section on Recent Progress in Electrical Modeling and Simulation of High-Speed ICs and Packages

Nov. 2010

Waveform Relaxation Time Domain Solver for Subsystem Arrays

Nov. 2010

In this paper we present a waveform relaxation approach for the transient analysis of 3-D electromagnetic problems using the partial element equivalent circuit (PEEC) method. Relying on weaker couplings among separated systems, a waveform relaxation scheme is proposed to accelerate the transient analysis of large electromagnetic problems. The results are compared with those obtained using a conventional PEEC formulation. They exhibit a significant speed-up while preserving the solution accuracy.

A Flexible Time-Stepping Scheme for Hybrid Field-Circuit Simulation Based on the Extended Time-Domain Finite Element Method

Nov. 2010

This paper describes a flexible time-stepping scheme for a recently developed hybrid field-circuit solver based on the extended time-domain finite element method (TDFEM) to alleviate the limitation on the use of a system-wide global time-step size. The proposed time-stepping scheme generalizes the strict synchronous coupling mechanism between the FEM and circuit subsystems and allows the signals in the different subsystems to be tracked and sampled at different time-step sizes. The signals from a slow subsystem with a larger time-step size are extrapolated, when necessary, for updating the signals in a fast subsystem with a smaller time-step size. The capability of the hybrid field-circuit solver with the proposed time-stepping scheme is further enhanced by the application of a tree-cotree splitting technique to the FEM subsystem, which helps reduce the iteration count per time step for a preconditioned iterative solution when the time-step size of the FEM subsystem becomes relatively large. With the flexibility of choosing subsystem-specific time-step sizes, the proposed time-stepping scheme improves the computational efficiency of the existing TDFEM-based hybrid field-circuit solver especially when the computational cost associated with the slow subsystems is much higher than that associated with the fast subsystems.

A Thermal Simulation Process Based on Electrical Modeling for Complex Interconnect, Packaging, and 3DI Structures

Nov. 2010

To reduce the product development time and achieve first-pass silicon success, fast and accurate estimation of very-large-scale integration (VLSI) interconnect, packaging and 3DI (3D integrated circuits) thermal profiles has become important. Present commercial thermal analysis tools are incapable of handling very complex structures and have integration difficulties with existing design flows. Many analytical thermal models, which could provide fast estimates, are either too specific or oversimplified. This paper highlights a methodology, which exploits electrical resistance solvers for thermal simulation, to allow acquisition of thermal profiles of complex structures with good accuracy and reasonable computation cost. Moreover, a novel accurate closed-form thermal model is developed. The model allows an isotropic or anisotropic equivalent medium to replace the noncritical back-end-of-line (BEOL) regions so that the simulation complexity is dramatically reduced. Using these techniques, this paper introduces the thermal modeling of practical complex VLSI structures to facilitate thermal guideline generation. It also demonstrates the benefits of the proposed anisotropic equivalent medium approximation for real VLSI structures in terms of the accuracy and computational cost.

A Novel High-Capacity Electromagnetic Compression Technique Based on a Direct Matrix Solution

Nov. 2010

Electromagnetic solvers based on integral equations in conjunction with the method of moments or the partial element equivalent circuit method (PEEC) proved to be popular because of their efficiency and accuracy. There is one serious drawback of the integral equation approach: it often leads to a linear system involving a full matrix. Many efficient approaches have been proposed to overcome this, largely based on compressing the matrix-vector product operation and using an iterative solver. Iterative EM solvers, however, suffer from slow convergence, which does not have a totally reliable method to address; further, large multiple right-hand sides significantly increase the solving time. In this paper, we present a novel method to compress low rank sub-block matrixes into sparse matrix to be used with a direct sparse matrix solver to obtain an efficient high-capacity electromagnetic solver based on an integral equation formulation. The full-rank system matrix is represented in a hierarchical matrix format that has its sub-matrixes compressed with numerically controllable accuracy; it is then analytically converted to a sparse matrix which is further solved by a direct sparse matrix solver. Analytically this method results in O(N (log N)²) complexity for computing the inverse of a hierarchical matrix presented in Fig. 2 where N is the number of unknowns.

An LU Decomposition Based Direct Integral Equation Solver of Linear Complexity and Higher-Order Accuracy for Large-Scale Interconnect Extraction

Nov. 2010

A fast LU factorization of linear complexity is developed to directly solve a dense system of linear equations for the capacitance extraction of any arbitrary shaped 3-D structure embedded in inhomogeneous materials. In addition, a higher-order scheme is developed to achieve any higher-order accuracy for the proposed fast solver without sacrificing its linear computational complexity. The proposed solver successfully factorizes dense matrices that involve more than one million unknowns in fast CPU run time and modest memory consumption. Comparisons with state-of-the-art integral-equation-based capacitance solvers have demonstrated its clear advantages. In addition to capacitance extraction, the proposed LU solver has been successfully applied to large-scale full-wave extraction.

Electromagnetic Modeling of Through-Silicon Via (TSV) Interconnections Using Cylindrical Modal Basis Functions

Nov. 2010

This paper proposes an efficient method to model through-silicon via (TSV) interconnections, an essential building block for the realization of silicon-based 3-D systems. The proposed method results in equivalent network parameters that include the combined effect of conductor, insulator, and silicon substrate. Although the modeling method is based on solving Maxwell's equation in integral form, the method uses a small number of global modal basis functions and can be much faster than discretization-based integral-equation methods. Through comparison with 3-D full-wave simulations, this paper validates the accuracy and the efficiency of the proposed modeling method.

A Markov Chain Based Hierarchical Algorithm for Fabric-Aware Capacitance Extraction

Nov. 2010

In this paper, we propose a hierarchical algorithm to compute the 3-D capacitances of a large number of topologically different layout configurations that are all assembled from the same basic layout motifs. Our algorithm uses the boundary element method in order to compute a Markov transition matrix (MTM) for each motif. The individual motifs are connected together by building a large Markov chain. Such Markov chain can be simulated extremely efficiently using Monte Carlo simulations (e.g., random walks). The main practical advantage of the proposed algorithm is its ability to extract the capacitance of a large number of layout configurations in a complexity that is basically independent of the number of configurations. For instance, in a large 3-D layout example, the capacitance calculation of 1000 different configurations assembled from the same motifs is accomplished in the time required to solve independently two configurations, i.e., a 500 × speedup.

Physics-Based Gridding for Electrical Package Analysis Codes

Nov. 2010

This paper describes techniques and advances for mesh generation and refinement for the analysis of electrical package structures. After a brief review of meshing techniques, a physically based justification is provided for the basic elements of gridding required to accurately represent the following physical issues: edge-effects, projection gridding for signal return currents, conductor proximity, skin-effect, frequency effects, and dielectrics. These individual gridding components are then incorporated into a comprehensive, global algorithm. Many other meshing issues are addressed, including constraints associated with the underlying electromagnetic calculation kernel, removal of superfluous grid lines, assuring symmetric results for symmetric structures, and consistency related to causality and nonphysical effects. A number of 2D and 3D examples are taken from various codes developed by the author and novel techniques are given for effectively gridding 2D structures having even extreme geometric aspect ratios.

Random Rough Surface Effects on Wave Propagation in Interconnects

Nov. 2010

To address the rough surface effects in high-speed interconnects on printed circuit boards (PCBs) and microelectronic packages, we study the electromagnetic wave propagation in a rough surface environment. In our model, the rough surface is characterized by a stochastic random process with correlation function or spectral density. This paper reviews the analytical theory, numerical simulations and experimental results based on such a model. We describe the rough surface characterization and the extraction of roughness parameters from 3D profile measurements. Initially we study the 2D case with the rough surface height function varying in only one horizontal direction and consider the case of plane wave incidence. Analytic second-order small perturbation method (SPM2) was used to obtain simple closed-form expressions for the absorption enhancement factor. The numerical transfer matrix (T-matrix) method and the method of moments (MoM) were also used. We next consider the case of the 3D problem with the rough surface height varying in both horizontal directions. We also used SPM2 to obtain a simple closed form expression for the enhancement factor. In interconnect problems, electromagnetic (EM) waves propagate in a guided wave environment. Thus, we next considered a waveguide model to study the effects of random roughness on wave propagation and compare with results from the plane wave formulation. Analytic SPM2 and numerical finite element method (FEM) with mode matching were used to obtain the enhancement factor. We also describe experimental results and correlation with the theoretical models. Finally, we explain how the enhancement factor concept used throughout lends itself to direct inclusion of rough surface effects in a wide variety of modeling problems.

Accurate Characterization of Broadband Multiconductor Transmission Lines for High-Speed Digital Systems

Nov. 2010

Accurate modeling of transmission lines becomes increasingly important in high-speed interconnect system design. However, it is rather difficult to obtain broadband transmission line models, in particular using frequency-domain measurements. This paper points out two potential accuracy issues. First, inaccurate DC values of the frequency-domain data cause a severe error in the time-domain simulations. Second, it is difficult to characterize the characteristic impedance over a wide frequency range due to the reflection caused by the port discontinuities. This paper proposes the combination of both time and frequency measurement data to mitigate the DC accuracy issue. For the characteristic impedance model, a new de-embedding technique is presented to mitigate the port discontinuity issue. Several numerical examples, such as MCM-L coplanar lines and package microstrip lines, are studied to validate the accuracy of the proposed method.

A Pluggable Large Core Step Index Plastic Optical Fiber With Built-In Mode Conditioners for Gigabit Ultra Short Reach Networks

Nov. 2010

Large core step-index plastic optical fibers (SI-POF) are bandwidth limited due to their high modal dispersion and coupling loss at the receiver. To date, the large core SI-POF are typically deployed up to 150 Mb/s applications. This paper reports the transmission of 2.5 Gb/s on 980 μm core step-index plastic optical fiber with fiber-based mode conditioning elements that are part of the connector assembly. The built-in mode conditioners are tapered fiber tips that provide restricted mode launching at transmitter and mode filtering at the receiver side. The structures, at the tip of POF, are optimized by optical simulations and fabricated using laser fusion process. The connector assembly is realized by precisely encapsulating the mode conditioners with a metallic ferrule and positioned using optical grade epoxies. These plug-in modules are inserted to a typical SFP transceiver LC connector receptacle and characterized for gigabit rates.

Proximity Lithography in Sub-10 Micron Circuitry for Packaging Substrate

Nov. 2010

Rapid changes in the semiconductor industry will continue toward higher functionality that leads to higher input/outputs (I/O) counts, pushing packaging towards higher density architectures. In the next two to three years, the I/O pitch will fall within 100 μm for area array die and 30 μm for periphery die. That raises an important question to the packaging industry: How will the rapid shrinkage of the I/O pitch affect the package substrate for chip attaching? The answer is sub-10 micron copper line technology. Theoretical and experimental studies on the limitations of using mercury i-line ultraviolet photolithography have been carried at the Packaging Research Center at Georgia Tech. Furthermore, ultra fine copper line routing substrates are demonstrated for flip chip attaching by using semi-additive metallization process.

A 3-D X-Band T/R Module Package With an Anodized Aluminum Multilayer Substrate for Phased Array Radar Applications

Nov. 2010

This paper presents the design and development of a compact 3-D transmit/receive (T/R) module with a selectively anodized aluminum multilayer package for X-band phased array radar applications. The proposed multilayer package consists of anodized aluminum substrates and vertical interconnects with embedded vias. The proposed package platform is based on thick anodized aluminum oxide layers and active bare chips directly mounted on bulk aluminum substrates for high electrical isolation and an effective heat sink. With its combination of thin-film embedded passive components and multilayer structure, the proposed module features a compact size of 20 mm × 20 mm, with a package height of 3.7 mm. To transfer radio-frequency (RF) signals vertically, we used coaxial hermetic seal vias with characteristic 50 Ω impedances and embedded anodized aluminum vias with a solder ball attachment and flip-chip bonding. The optimized vertical interconnect structure demonstrates RF characteristics with an insertion loss of less than 1.55 dB and a return loss of less than 12.25 dB over a broad bandwidth ranging from 0.1 to 10 GHz. The fabricated X-band 3-D T/R module has a maximum transmit output power of 39.81 dBm (9.5 W), a maximum transmit gain of 41.25 dB, and a receive gain of 19.15 dB over the 9-10 GHz frequency band. The RF-signal phase amplitude control is achieved by means of a 6 bit phase shifter with an rms accuracy of more than 5° and a gain setting range of 24 dB with an rms accuracy of more than 1.5 dB. The proposed multilayer aluminum package has the advantages of reducing the module size, decreasing the cost, and managing the thermal problem for X-band high-power T/R module package applications.

Interfacial Design of Anisotropic Conductive Adhesive Based Interconnects Using Molecular Wires and Understanding of Their Electrical Conduction

Nov. 2010

Anisotropic conductive adhesives (ACAs) have been considered a promising interconnect material for next generation high performance devices. However, high joint resistance and low current carrying capability of ACA interconnects have been the limitations to utilizing ACAs in high power devices. In this study, we have introduced conjugated dithiols into ACA formulations to create molecular wire junctions between conductive fillers and metal pads as a means to facilitate the electron transport through the ACA joints. With the introduction of molecular wires, there is evidence of measured improvements in both the electrical conductivity and current carrying capability. The factors leading to these improvements in electrical properties are also discussed.

A Homogeneous Electrically Conductive Silver Paste

Nov. 2010

A homogeneous electrically conductive silver paste was developed using silver i-propylcarbamate ((CH₃)₂CHNHCOOAg) as the precursor of functional phase. The precursor had good solubility in water and methanol, high silver content (about 50 wt.%) and low decomposition temperature (below 200 °C). The paste was a non-Newtonian fluid with the viscosity depending significantly on the content of thickening agent (ethyl cellulose). When the paste was applied in micro-pen direct-writing process, it was able to produce high-resolution (20 μm or so) array patterns. After a homogeneous paste with about 40 wt.% silver i-propylcarbamate as the precursor was directly written and sintered at 180 °C for 15 min, an electrically conductive network consisting of more than 95 wt.% silver was formed and the network had a volume electrical resistivity in the order of magnitude of 10^-5-10^-6 Ω · cm and a sheet electrical resistivity in the order of magnitude of 10^-4 Ω/square.

Wafer-Level Vacuum Packaging of Micromachined Thermoelectric IR Sensors

Nov. 2010

In the trend towards low-cost, high-performance, and miniaturization, a wafer-level vacuum package is developed for micromachined thermoelectric infrared (IR) sensor. An IR sensor wafer and a cap wafer are bonded together in a vacuum chamber using Au-Au thermocompression bonding, where the cap wafer not only protects the floating thermopile structure but also selects IR light for the sensor. The device fabrication and Au-Au thermocompression hermetic bonding process as well as the packaged IR sensor characterization is presented in this paper. Experimental results show that the wafer-level vacuum packaged IR sensor has a four times higher responsivity and detectivity than the IR sensor with atmosphere pressure package, which confirms the IR performance improvement due to vacuum packaging. IR microscope image of the packaged device proved that the Au-Au thermocompression bonding process is compatible to the handling of fragile micromachined thermopile structure. Average leak rate and shear strength are, respectively, 3.9 × 10^-9 atm cc/s and 16.709 Kgf, which shows that the Au-Au thermocompression hermetic bonding is suitable for the wafer-level vacuum packaging of micromachined thermoelectric IR sensor.

Sn Bumping Without Photoresist Mould and Si Dice Stacking for 3-D Packaging

Nov. 2010

Chip stacking with through-silicon-vias (TSV) technology for 3-D packaging of electronic devices was investigated. A new process of direct solder bumping on Si wafers without photoresist (PR) mould was designed and applied in this study. The Cu extrusion process on the via was also omitted for process simplification. This simplified process can be useful for cost reduction and increased productivity. The substrate for the experiments was a p-type 〈100 〉 Si wafer of 100 mm diameter. In order to produce the vias, the Si wafer was etched by a deep reactive ion etcher (DRIE) using SF₆ and C₄F₈ plasmas alternately. The produced vias were 40 μm in diameter and 80 μm in depth. On the via side walls, SiO₂, Ti, and Au layers were formed with thicknesses of 1, 0.1, and 0.7μm, respectively. Pulsed direct current (DC) electroplating was used to fill the vias with Cu. Then the Si wafer was back ground to a thickness of 80 μm until the Cu filling in the vias was exposed to the surface without extrusion. Plating current subsequently flowed through the vias to the bumping surface, and Sn was electroplated on the Cu filling directly without a PR mould. To optimize the bumping process, the current density and time for Sn plating were varied from 0.04 to 0.06 A/cm² and from 10 to 40 min, respectively. Bumps with a height of 20 μm were formed successfully with 0.05 A/cm² and 30 min without a PR mould. The bump height increased with increasing plating current and time; for example, from 13 μm at 10 min to 33 μm at 40 min in case of 0.06 A/cm². The Si dice with electroplated Sn bumps had dimensions of 5 × 5 mm and thickness of 80 μm. Three Si dice were stacked successfully by micro-soldering at 260°C. In the interface between the Sn bumps and the Cu filling, a Cu₆Sn₅ intermetallic compound was pr- - oduced with a thickness of 3.2 μm. Through this study, a process for non-PR solder bumping by electroplating and wafer stacking with TSV was achieved successfully.

Issues in the Use of Thermal Transients to Achieve Accurate Time-Constant Spectrums and Differential Structure Functions

Nov. 2010

An analysis of accuracy of time-constant spectrum extraction from thermal transients has been performed. Numerical calculations based on analytical models and finite element method simulations have been used in order to obtain the thermal transients. Simple geometries have been used such that analytical expressions for their time-constant spectrums are known. Results show that a large error in the time-constant spectrum is obtained for very small rms error (<;1 mK) in the thermal transient. The estimation problem is ill-conditioned. Moreover, the differential structure function shows a low accuracy identifying stacked structures. The initial part of the differential structure function shows numerical oscillations and the final part has an asymptotic behavior to infinity that has been identified as an artifact related to errors in the time-constant spectrum estimation. Peak identification from the differential structure function heavily depends on an accurate determination of the time-constant spectrum. The limited spectral resolution and dynamic range of the differential structure function are a direct consequence of the time-constant spectrum imprecision.

Transient Thermal Network Modeling Applied to Multiscale Systems. Part I: Definition and Validation

Nov. 2010

This paper formulates the methodology of transient thermal network modeling (TTNM) for the study of unsteady heat transfer in systems where the presence of multiple length and time scales prevents the analysis by means of current computational or experimental techniques. The TTNM is based on reduced order models (ROMs) and it is established under the essential premise that a transient heat transfer process can be modeled by its division in a succession of stationary states and the division of the geometry in isothermal elements, according to the characteristic time and length scales obtained by scale analysis. The methodology is subsequently validated with canonical examples and considerations are given for the application to practical problems.

Transient Thermal Network Modeling Applied to Multiscale Systems. Part II: Application to an Electronic Control Unit of an Automobile

Nov. 2010

This paper applies the methodology of transient thermal network modelling (TTNM) introduced in Part I to the heat transfer analysis of an electronic control unit (ECU) located in the engine enclosure of a motorcar. The complexity of the geometry, the diverse heat transfer mechanisms involved and the duration of the operating cycle prevent the use of both simple, lumped models and detailed numerical simulations. The TTNM methodology relies instead in steady, approximate heat transfer correlations and a division of the system into the largest possible isothermal elements, based on the analysis of characteristic time and length scales. The dynamic heat balance of each element is then written down, conforming the TTNM of the system, which is numerically integrated with an adequate time step. The practical aspects of the TTNM methodology (design stage) are finally demonstrated; in this particular case-study, the model reveals a very high risk of damage of electronic components due to the radiative heat load received from the exhaust pipe of the engine. A design modification consisting of a radiative shield is proposed and model-tested, achieving an appropriate reduction of heat flux and temperatures, and thus an adequate protection of critical components.

Compromise Impedance Match Design for Pogo Pins With Different Single-Ended and Differential Signal-Ground Patterns

Nov. 2010

A new concept of compromise impedance match design is proposed for pogo pins with various signal-ground patterns. To begin with, the methodologies of equivalent circuit modeling for single-ended and differential pogo pins are described. A de-embedding technique is proposed to eliminate the effect of a specialized test fixture for the characterization of the pogo pins. Good agreement is found from the comparison between measured and simulated results, which validates the modeling and simulation methodologies. Then, the reflection of pogo pins with various signal-ground patterns is investigated and the optimal pin radius to pitch ratio is found to be 0.20-0.21, thereby achieving a return loss better than 15 dB for all these patterns in both single-ended and differential configurations from dc to 10 GHz. In addition, the effects of pin length are considered and a general design chart is constructed for determining the pogo pin geometry and the applicable impedance range to meet the specification on the return loss. Several compromise impedance design applications demonstrating the proposed methods are given.

Enhanced Microstrip Guard Trace for Ringing Noise Suppression Using a Dielectric Superstrate

Nov. 2010

Grounded guard traces are increasingly used to reduce the coupling-induced crosstalk, but the incurred ringing noise will strongly limit the performance for the microstrip structures. This paper describes the generation mechanism of the ringing noise and derives an analytical formula of the noise magnitude. Besides, an enhanced microstrip guard trace design is proposed to eliminate the ringing noise by covering the original microstrip structure with a superstrate of higher permittivity. A design space versus the superstrate thickness and the dielectric constant are constructed and in which, the guard trace needs be grounded at the two ends only without causing any ringing noise. Finally, the time-domain simulations and experiments are performed to verify the proposed concept.

A Wideband Common-Mode Suppression Filter for Bend Discontinuities in Differential Signaling Using Tightly Coupled Microstrips

Nov. 2010

A new type of bend is proposed that reduces differential-to-common mode conversion occuring at the bend discontinuity in coupled microstrip lines for high-speed digital circuits. Simultaneously, great care has been taken to minimize the differential reflection coefficient and insertion loss, leading to an overall improved signal integrity. This is achieved by tapering the microstrip lines to tightly or very tightly coupled ones in the area of the bend. Full-wave simulations in the DC to 6 GHz frequency range show that over 9 dB and 14 dB suppression of conversion noise is achieved for tightly coupled and very tightly coupled bends, respectively. Also for these new structures, with a total length of 100 mm, the insertion loss remains below 0.6 dB. Measurements on prototype bends show very good agreement with full-wave simulations. Also time domain measurements demonstrate the significant reduction in conversion noise while keeping return loss low. Moreover, for design purposes, a dedicated circuit model which closely matches the full-wave characteristics of the proposed bends is presented.

Self-Consistent Simulation of Opto-Electronic Circuits Using a Modified Nodal Analysis Formulation

Nov. 2010

This paper addresses the need for self-consistent simulation of mixed electrical and optical circuits and systems. Drawing on the use of modified nodal analysis (MNA) techniques ubiquitous in circuit simulation, an optical node is formulated which includes the magnitude and phase of the optical signal being simulated. This node consists of two propagating complex envelopes one for the forward direction and the other for the reverse direction. Using this formulation models are developed for a variety of devices including: lasers, photodiodes, multimode fiber, and optical connectors. The formulation allows for definition of multiple optical channels at different carrier frequencies, enables quick simulation of systems with large optical delays and optical interference effects. Several numerical examples are presented in this paper to illustrate the capability of the proposed framework and where practicable the results were compared to commercial simulators. These examples include a multimode fiber optical link, an integrated array of laser sources and a feedback controlled laser source used in a optical link with modulation achieved by the use of an electro-absorption device.

Design of a Common Mode Filter by Using Planar Electromagnetic Bandgap Structures

Nov. 2010

In this paper, an embedded electromagnetic bandgap structure is proposed for harmonic filtering of differential signal's undesired common mode components. Rather than use lumped circuit components and likely causing some degradation to the intended high speed differential signal, the embedded planar common mode filter causes no degradation to the intended signal, and enhances the signal integrity and electromagnetic compatibility performance of the system. Single ended and differential traces are considered and the impact of the common mode filtering is measured in terms of mixed mode scattering parameters and eye diagram metrics. The systematic procedure to design such a structure is outlined, and its design robustness is also verified.

Multiparameter Sensitivity Analysis of Multiple Coupled Vias in Board and Package Structures for Early Design and Optimization

Nov. 2010

Analytical expressions for the multiparametric sensitivity analysis of coupled-via S -parameters in board and package structures are derived in this paper. These expressions are validated with finite difference approximations of S-parameters obtained from three-dimensional field solvers and of the analytical expressions themselves. Sensitivity analysis with respect to multiple geometric and material variations provides quick early-design insight without resorting to complete three-dimensional field simulation. Sensitivities for eccentric effect of via drilling and exterior problem are also studied. First derivative data is also critical for gradient-based optimization of system-level performance which includes via-via coupling. The proposed approach is a stepping stone towards early design and optimization for large-scale via structures in microelectronics systems.

Parameterized Model Order Reduction of Electromagnetic Systems Using Multiorder Arnoldi

Nov. 2010

This paper presents an efficient algorithm to create parametric reduced order models of distributed electromagnetic systems that have arbitrary functions of frequency (due to material properties, boundary conditions, delay elements) and design parameters. The proposed method is based on a multiorder Arnoldi algorithm used to implicitly calculate the moments with respect to frequency and design parameters, as well as the cross-moments. This procedure generates parametric reduced order models that are valid over the desired parameter range without the need to redo the reduction when design parameters are changed. Numerical examples are provided to illustrate the validity of the proposed algorithm.

A Hierarchical Simulation Flow for Return-Loss Optimization of Microprocessor Package Vertical Interconnects

Nov. 2010

Design of package- and board-level interconnects utilizing full-wave electromagnetic solvers, is becoming increasingly important owing to increased frequencies of operation, miniaturization, and reduced time to market. Thus, parameterization, optimization, and statistical analysis tools are becoming an invaluable part of a designer's armory. Leveraging a previously developed fast full-wave electromagnetic solver, this paper addresses the development of a framework for package interconnect design. Parametric sweeps are conducted to show the existence of optimal designs and to select the best routing strategies. Having applied the popular response surface methodology for optimization and having outlined its limitations for higher-dimensional problems, a general optimization scheme is proposed and illustrated on a differential package interconnect line. The proposed methodology features a dimensionality reduction scheme and a reusable, multidimensional look-up table preceding the global optimization phase, which is facilitated by a smooth interpolation scheme based on splines. The second phase features a custom local optimizer incorporating all the variables without any dimension reduction. This methodology has been applied to automated synthesis of a differential package line resulting in a significant improvement of the return loss performance. A statistical analysis methodology, based on utilizing the gradient, has been presented to arrive at the spread in the differential return loss, occurring due to manufacturing tolerances, around the designed response.

Passivity Check of $S$ -Parameter Descriptor Systems via $S$ -Parameter Generalized Hamiltonian Methods

Nov. 2010

This paper extends the generalized Hamiltonian method (GHM) (Zhang , 2009; Zhang and Wong, 2010) and its half-size variant (HGHM) (Zhang and Wong, 2010) to their S -parameter counterparts (called S-GHM and S-HGHM, respectively), for testing the passivity of S -parameter descriptor-form models widely used in high-speed circuit and electromagnetic simulations. The proposed methods are capable of accurately detecting the possible nonpassive regions of descriptor-form models with either scattering or hybrid (impedance or admittance) transfer matrices. Their effectiveness and accuracy are verified with several practical examples. The S-GHM and S-HGHM methods presented here provide a foundation for the passivity enforcement of S-parameter descriptor systems.

A Theoretically Rigorous Full-Wave Finite-Element-Based Solution of Maxwell's Equations From dc to High Frequencies

Nov. 2010

It has been observed that finite element based solutions of full-wave Maxwell's equations break down at low frequencies. In this paper, we present a theoretically rigorous method to fundamentally eliminate the low-frequency breakdown problem. The key idea of this method is that the original frequency-dependent deterministic problem can be rigorously solved from a generalized eigenvalue problem that is frequency independent. In addition, we found that the zero eigenvalues of the generalized eigenvalue problem cannot be obtained as zeros because of finite machine precision. We hence correct the inexact zero eigenvalues to be exact zeros. The validity and accuracy of the proposed method have been demonstrated by the analysis of both lossless and lossy problems having on-chip circuit dimensions from dc to high frequencies. The proposed method is applicable to any frequency. Hence it constitutes a universal solution of Maxwell's equations in a full electromagnetic spectrum. The proposed method can be used to not only fundamentally eliminate the low-frequency breakdown problem, but also benchmark the accuracy of existing electromagnetic solvers at low frequencies including static solvers. Such a benchmark does not exist yet because full-wave solvers break down while static solvers involve theoretical approximations.

Guard Trace Design for Improvement on Transient Waveforms and Eye Diagrams of Serpentine Delay Lines

Nov. 2010

This paper investigates the utilization of the guard traces to improve the eye opening and jitter for serpentine delay lines. It is found that the guard trace can reduce the original time-domain transmission (TDT) and time-domain reflection (TDR) crosstalk noises by more than 50%, if shorted by only two grounded vias at both ends of the trace. The time domain analysis as well as the associated simple circuit modeling is presented to explain the occurrence of noise cancellation mechanism on the guard trace. In addition, narrow signal trace is proposed to improve the TDR waveform by compensating the impedance mismatch due to the inserted guard traces. Finally, the HSPICE simulation and time-domain measurements of crosstalk noises, TDR/TDT waveforms, and eye diagrams are performed to validate the proposed analysis and design.

High Quality and Low Loss Millimeter Wave Passives Demonstrated to 77-GHz for SiP Technologies Using Embedded Wafer-Level Packaging Platform (EMWLP)

Nov. 2010

With the increasing demand for system integration to cater to continuously increasing number of I/Os as well as higher operating frequencies, reconfigured wafer-level packaging, or embedded WLP (EMWLP) is emerging as a promising technology for integration. This platform allows integrated passives to be designed in the redistribution layers using the mold compound as a substrate, which significantly improves the passives performance compared to those of on-chip. In this paper, we present low loss passives on EMWLP platform demonstrated in a 5.5-GHz band pass filter targeted for wireless local area network (WLAN) applications. To ascertain the feasibility of designing for low loss millimeter wave passives on EMWLP, transmission lines were designed and their loss characteristics investigated up to 110 GHz, which are reported here. Subsequently we demonstrate for the first time a narrowband low loss 77-GHz band pass filter on EMWLP platform, with a good correlation obtained between simulation and measurement results. In addition, a temperature dependence characterization was performed on the 77-GHz filter, with little variation in the measured filter characteristics observed.

RF Characterization and Analytical Modelling of Through Silicon Vias and Coplanar Waveguides for 3D Integration

Nov. 2010

High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been electrically characterized in the direct current (dc) and microwave regimes for 3D interconnect applications. The vias were micro-machined in silicon, insulated, and filled with copper employing a bottom-up copper electroplating technique in a “via-first” approach. DC via resistance measurements show good agreement with the theoretical expected value (~ 16 mΩ) . Radio-frequency (RF) measurements up to 50 GHz have been performed on coplanar waveguides located on the back-side of the wafers and connected to the front-side with TSVs. The S-parameters indicate clearly the beneficial impact of double sided ground planes of the RF signals. The via resistance extracted from impedance measurements is in good agreement with dc values, while the inductance (53 pH) and capacitance (2.4 pF) of the TSV are much lower than conventional wire bonding, which makes the use of TSV very promising for 3D integration. An advanced analytical model is proposed for the interconnect system with vias and lines and shows very good agreement with the experimental data with a limited number of fitting parameters. This work gives a proof of concept for high aspect ratio TSV manufacturing and new insights to improve 3D interconnect modeling for systems-in-package applications in the microwave regime.

Design of a Controllable Delay Line

Nov. 2010

Delay lines are used in printed circuit boards (PCBs) to produce delay between two points (or devices) while occupying as little board space as possible. As higher clock frequency is used in circuits, electromagnetic coupling between adjacent traces of delay line increases. The coupling that takes place between all the parallel adjoining traces combines synchronously or asynchronously to cause dispersion. Consequently, simple analytic techniques that predict delay line behavior are ineffective to predict precise delay and costly full-wave modeling or measurement becomes essential. In this paper, we consider microstrip meander delay lines and study the effect of the number of segments on resulting delay using full-wave modeling and measurement. We show that for short segments and when the number of segments is large enough, the resulting delay per segment is almost uniform and does not change as the number of segments increases. We show a linear relationship between the number of segments and the total delay, thus allowing for simple delay line design without the prohibitive cost of full-wave three-dimensional modeling of the entire delay line structure. Demonstration of these findings is supported by numerical simulations and experimental measurement.

Nov. 2010

2010 Index IEEE Transactions on Advanced Packaging Vol. 33

Nov. 2010

This index covers all technical items - papers, correspondence, reviews, etc. - that appeared in this periodical during the year, and items from previous years that were commented upon or corrected in this year. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name. The primary entry includes the coauthors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, month, and year, and inclusive pages. Note that the item title is found only under the primary entry in the Author Index.

IEEE Components, Packaging, and Manufacturing Technology Society Information for authors

Nov. 2010

Provides instructions and guidelines to prospective authors who wish to submit manuscripts.

IEEE Components, Packaging, and Manufacturing Technology Society Information

Nov. 2010

Advanced Packaging, IEEE Transactions on - new TOC

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IEEE Transactions on Advanced Packaging publication information

Editorial CPMT Society to Merge Transactions in 2011

Our Thanks to Reviewers IEEE Transactions on Advanced Packaging

Foreword Special Section on Recent Progress in Electrical Modeling and Simulation of High-Speed ICs and Packages

Waveform Relaxation Time Domain Solver for Subsystem Arrays

A Flexible Time-Stepping Scheme for Hybrid Field-Circuit Simulation Based on the Extended Time-Domain Finite Element Method

A Thermal Simulation Process Based on Electrical Modeling for Complex Interconnect, Packaging, and 3DI Structures

A Novel High-Capacity Electromagnetic Compression Technique Based on a Direct Matrix Solution

An LU Decomposition Based Direct Integral Equation Solver of Linear Complexity and Higher-Order Accuracy for Large-Scale Interconnect Extraction

Electromagnetic Modeling of Through-Silicon Via (TSV) Interconnections Using Cylindrical Modal Basis Functions

A Markov Chain Based Hierarchical Algorithm for Fabric-Aware Capacitance Extraction

Physics-Based Gridding for Electrical Package Analysis Codes

Random Rough Surface Effects on Wave Propagation in Interconnects

Accurate Characterization of Broadband Multiconductor Transmission Lines for High-Speed Digital Systems

A Pluggable Large Core Step Index Plastic Optical Fiber With Built-In Mode Conditioners for Gigabit Ultra Short Reach Networks

Proximity Lithography in Sub-10 Micron Circuitry for Packaging Substrate

A 3-D X-Band T/R Module Package With an Anodized Aluminum Multilayer Substrate for Phased Array Radar Applications

Interfacial Design of Anisotropic Conductive Adhesive Based Interconnects Using Molecular Wires and Understanding of Their Electrical Conduction

A Homogeneous Electrically Conductive Silver Paste

Wafer-Level Vacuum Packaging of Micromachined Thermoelectric IR Sensors

Sn Bumping Without Photoresist Mould and Si Dice Stacking for 3-D Packaging

Issues in the Use of Thermal Transients to Achieve Accurate Time-Constant Spectrums and Differential Structure Functions

Transient Thermal Network Modeling Applied to Multiscale Systems. Part I: Definition and Validation

Transient Thermal Network Modeling Applied to Multiscale Systems. Part II: Application to an Electronic Control Unit of an Automobile

Compromise Impedance Match Design for Pogo Pins With Different Single-Ended and Differential Signal-Ground Patterns

Enhanced Microstrip Guard Trace for Ringing Noise Suppression Using a Dielectric Superstrate

A Wideband Common-Mode Suppression Filter for Bend Discontinuities in Differential Signaling Using Tightly Coupled Microstrips

Self-Consistent Simulation of Opto-Electronic Circuits Using a Modified Nodal Analysis Formulation

Design of a Common Mode Filter by Using Planar Electromagnetic Bandgap Structures

Multiparameter Sensitivity Analysis of Multiple Coupled Vias in Board and Package Structures for Early Design and Optimization

Parameterized Model Order Reduction of Electromagnetic Systems Using Multiorder Arnoldi

A Hierarchical Simulation Flow for Return-Loss Optimization of Microprocessor Package Vertical Interconnects

Passivity Check of -Parameter Descriptor Systems via -Parameter Generalized Hamiltonian Methods

A Theoretically Rigorous Full-Wave Finite-Element-Based Solution of Maxwell's Equations From dc to High Frequencies

Guard Trace Design for Improvement on Transient Waveforms and Eye Diagrams of Serpentine Delay Lines

High Quality and Low Loss Millimeter Wave Passives Demonstrated to 77-GHz for SiP Technologies Using Embedded Wafer-Level Packaging Platform (EMWLP)

RF Characterization and Analytical Modelling of Through Silicon Vias and Coplanar Waveguides for 3D Integration

Design of a Controllable Delay Line

Table of contents

Table of contents

2010 Index IEEE Transactions on Advanced Packaging Vol. 33

IEEE Components, Packaging, and Manufacturing Technology Society Information for authors

IEEE Components, Packaging, and Manufacturing Technology Society Information

Passivity Check of $S$ -Parameter Descriptor Systems via $S$ -Parameter Generalized Hamiltonian Methods