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TOC Alert for Publication# 6040 2012January 03<![CDATA[Table of contents]]>334C175353<![CDATA[IEEE Transactions on Advanced Packaging publication information]]>334C2C240<![CDATA[Editorial CPMT Society to Merge Transactions in 2011]]>334754755163<![CDATA[Our Thanks to Reviewers IEEE Transactions on Advanced Packaging]]>33475675727<![CDATA[Foreword Special Section on Recent Progress in Electrical Modeling and Simulation of HighSpeed ICs and Packages]]>334758759179<![CDATA[Waveform Relaxation Time Domain Solver for Subsystem Arrays]]>334760768927<![CDATA[A Flexible TimeStepping Scheme for Hybrid FieldCircuit Simulation Based on the Extended TimeDomain Finite Element Method]]>334769776886<![CDATA[A Thermal Simulation Process Based on Electrical Modeling for Complex Interconnect, Packaging, and 3DI Structures]]>3347777861467<![CDATA[A Novel HighCapacity Electromagnetic Compression Technique Based on a Direct Matrix Solution]]>2) complexity for computing the inverse of a hierarchical matrix presented in Fig. 2 where N is the number of unknowns.]]>334787793502<![CDATA[An LU Decomposition Based Direct Integral Equation Solver of Linear Complexity and HigherOrder Accuracy for LargeScale Interconnect Extraction]]>3347948031015<![CDATA[Electromagnetic Modeling of ThroughSilicon Via (TSV) Interconnections Using Cylindrical Modal Basis Functions]]>3348048172283<![CDATA[A Markov Chain Based Hierarchical Algorithm for FabricAware Capacitance Extraction]]>3348188271026<![CDATA[PhysicsBased Gridding for Electrical Package Analysis Codes]]>334828838818<![CDATA[Random Rough Surface Effects on Wave Propagation in Interconnects]]>3348398561297<![CDATA[Accurate Characterization of Broadband Multiconductor Transmission Lines for HighSpeed Digital Systems]]>3348578671408<![CDATA[A Pluggable Large Core Step Index Plastic Optical Fiber With BuiltIn Mode Conditioners for Gigabit Ultra Short Reach Networks]]>334868875896<![CDATA[Proximity Lithography in Sub10 Micron Circuitry for Packaging Substrate]]>3348768821329<![CDATA[A 3D XBand T/R Module Package With an Anodized Aluminum Multilayer Substrate for Phased Array Radar Applications]]>3348838911848<![CDATA[Interfacial Design of Anisotropic Conductive Adhesive Based Interconnects Using Molecular Wires and Understanding of Their Electrical Conduction]]>334892898639<![CDATA[A Homogeneous Electrically Conductive Silver Paste]]>3)_{2}CHNHCOOAg) as the precursor of functional phase. The precursor had good solubility in water and methanol, high silver content (about 50 wt.%) and low decomposition temperature (below 200 °C). The paste was a nonNewtonian fluid with the viscosity depending significantly on the content of thickening agent (ethyl cellulose). When the paste was applied in micropen directwriting process, it was able to produce highresolution (20 μm or so) array patterns. After a homogeneous paste with about 40 wt.% silver ipropylcarbamate as the precursor was directly written and sintered at 180 °C for 15 min, an electrically conductive network consisting of more than 95 wt.% silver was formed and the network had a volume electrical resistivity in the order of magnitude of 10^{5}10^{6} Ω · cm and a sheet electrical resistivity in the order of magnitude of 10^{4} Ω/square.]]>3348999031719<![CDATA[WaferLevel Vacuum Packaging of Micromachined Thermoelectric IR Sensors]]>9 atm cc/s and 16.709 Kgf, which shows that the AuAu thermocompression hermetic bonding is suitable for the waferlevel vacuum packaging of micromachined thermoelectric IR sensor.]]>3349049111178<![CDATA[Sn Bumping Without Photoresist Mould and Si Dice Stacking for 3D Packaging]]>6 and C_{4}F_{8} plasmas alternately. The produced vias were 40 μm in diameter and 80 μm in depth. On the via side walls, SiO_{2}, Ti, and Au layers were formed with thicknesses of 1, 0.1, and 0.7μm, respectively. Pulsed direct current (DC) electroplating was used to fill the vias with Cu. Then the Si wafer was back ground to a thickness of 80 μm until the Cu filling in the vias was exposed to the surface without extrusion. Plating current subsequently flowed through the vias to the bumping surface, and Sn was electroplated on the Cu filling directly without a PR mould. To optimize the bumping process, the current density and time for Sn plating were varied from 0.04 to 0.06 A/cm^{2} and from 10 to 40 min, respectively. Bumps with a height of 20 μm were formed successfully with 0.05 A/cm^{2} and 30 min without a PR mould. The bump height increased with increasing plating current and time; for example, from 13 μm at 10 min to 33 μm at 40 min in case of 0.06 A/cm^{2}. The Si dice with electroplated Sn bumps had dimensions of 5 × 5 mm and thickness of 80 μm. Three Si dice were stacked successfully by microsoldering at 260°C. In the interface between the Sn bumps and the Cu filling, a Cu_{6}Sn_{5} intermetallic compound was pr

oduced with a thickness of 3.2 μm. Through this study, a process for nonPR solder bumping by electroplating and wafer stacking with TSV was achieved successfully.]]>3349129171537<![CDATA[Issues in the Use of Thermal Transients to Achieve Accurate TimeConstant Spectrums and Differential Structure Functions]]>334918923790<![CDATA[Transient Thermal Network Modeling Applied to Multiscale Systems. Part I: Definition and Validation]]>334924937795<![CDATA[Transient Thermal Network Modeling Applied to Multiscale Systems. Part II: Application to an Electronic Control Unit of an Automobile]]>3349389521900<![CDATA[Compromise Impedance Match Design for Pogo Pins With Different SingleEnded and Differential SignalGround Patterns]]>334953960736<![CDATA[Enhanced Microstrip Guard Trace for Ringing Noise Suppression Using a Dielectric Superstrate]]>3349619681340<![CDATA[A Wideband CommonMode Suppression Filter for Bend Discontinuities in Differential Signaling Using Tightly Coupled Microstrips]]>3349699782238<![CDATA[SelfConsistent Simulation of OptoElectronic Circuits Using a Modified Nodal Analysis Formulation]]>3349799931098<![CDATA[Design of a Common Mode Filter by Using Planar Electromagnetic Bandgap Structures]]>33499410022280<![CDATA[Multiparameter Sensitivity Analysis of Multiple Coupled Vias in Board and Package Structures for Early Design and Optimization]]>S parameters in board and package structures are derived in this paper. These expressions are validated with finite difference approximations of Sparameters obtained from threedimensional field solvers and of the analytical expressions themselves. Sensitivity analysis with respect to multiple geometric and material variations provides quick earlydesign insight without resorting to complete threedimensional field simulation. Sensitivities for eccentric effect of via drilling and exterior problem are also studied. First derivative data is also critical for gradientbased optimization of systemlevel performance which includes viavia coupling. The proposed approach is a stepping stone towards early design and optimization for largescale via structures in microelectronics systems.]]>334100310111736<![CDATA[Parameterized Model Order Reduction of Electromagnetic Systems Using Multiorder Arnoldi]]>33410121020726<![CDATA[A Hierarchical Simulation Flow for ReturnLoss Optimization of Microprocessor Package Vertical Interconnects]]>334102110331307<![CDATA[Passivity Check of <formula formulatype="inline"> <img src="/images/tex/397.gif" alt="S"> </formula>Parameter Descriptor Systems via <formula formulatype="inline"> <img src="/images/tex/397.gif" alt="S"> </formula>Parameter Generalized Hamiltonian Methods]]>S parameter counterparts (called SGHM and SHGHM, respectively), for testing the passivity of S parameter descriptorform models widely used in highspeed circuit and electromagnetic simulations. The proposed methods are capable of accurately detecting the possible nonpassive regions of descriptorform models with either scattering or hybrid (impedance or admittance) transfer matrices. Their effectiveness and accuracy are verified with several practical examples. The SGHM and SHGHM methods presented here provide a foundation for the passivity enforcement of Sparameter descriptor systems.]]>334103410421199<![CDATA[A Theoretically Rigorous FullWave FiniteElementBased Solution of Maxwell's Equations From dc to High Frequencies]]>33410431050767<![CDATA[Guard Trace Design for Improvement on Transient Waveforms and Eye Diagrams of Serpentine Delay Lines]]>334105110602211<![CDATA[High Quality and Low Loss Millimeter Wave Passives Demonstrated to 77GHz for SiP Technologies Using Embedded WaferLevel Packaging Platform (EMWLP)]]>334106110711953<![CDATA[RF Characterization and Analytical Modelling of Through Silicon Vias and Coplanar Waveguides for 3D Integration]]>33410721079980<![CDATA[Design of a Controllable Delay Line]]>33410801087730<![CDATA[Table of contents]]>3341088108839<![CDATA[Table of contents]]>3341089109047<![CDATA[2010 Index IEEE Transactions on Advanced Packaging Vol. 33]]>33410911108194<![CDATA[IEEE Components, Packaging, and Manufacturing Technology Society Information for authors]]>334C3C334<![CDATA[IEEE Components, Packaging, and Manufacturing Technology Society Information]]>334C4C431