http://ieeexplore.ieee.org TOC Alert for Publication# 5503868 2013 May 21 3 1 C1 C4 160 3 1 C2 C2 132 3 1 1 4 910 3 1 5 12 917 3 1 13 22 1880 S 8051) and a quasi-delay-insensitive asynchronous-logic (A 8051) 8051 microcontroller core are designed and fabricated for full-range DVS from nominal VDD to deep sub-threshold. The performance of the S 8051 and A 8051 are largely comparable at nominal conditions and the entire DVS range, but differs when PVT and workload are varied. At nominal VDD, both the microcontroller cores feature comparable energy and speed, with the electromagnetic interference of the A 8051 ~ 12 dB lower and the area ~ 2 × larger than the S 8051. When DVS is applied, both the microcontroller cores feature comparable energy and speed; the S 8051 requires simultaneous adjustment of clock frequency with VDD. At wide PVT variations, up to ~ 12 × delay margins are required for the S 8051, whereas the A 8051 operates at actual speed. When the workload of both microcontrollers is varied, the A 8051 features lower energy dissipation per workload due to the exploitation of its asynchronous-logic protocols. For IoT applications that incur wide PVT and workload variations, A 8051 is more suitable due to its self-timed nature, whereas when PVT and workload variations are less severe, S 8051 is more suitable due to a smaller IC area.]]> 3 1 23 34 3720 Vdd is an important parameter in any meaningful system control mechanism. Reliable and accurate on-chip voltage sensors are therefore indispensible for the power and computation management of such systems. Existing voltage sensing methods are not suitable because they usually require a stable and known reference (voltage, current, time, frequency, etc.), which is difficult to obtain in this environment. This paper describes an autonomous reference-free voltage sensor designed using an asynchronous counter powered by the charge on a capacitor and a small controller. Unlike existing methods, the voltage information is directly generated as a digital code. The sensor, fabricated in the 180 nm technology node, was tested successfully through performing measurements over the voltage range from 1.8 V down to 0.8 V.]]> 3 1 35 44 1795 3 1 45 54 1434 3 1 55 64 2069 3 1 65 74 1443 2 of silicon area (0.979 mm² after place and route) while it consumes 182.94 nW @ 1.08 V, estimated with Synopsys PrimeTime when operating at 1 KHz. These results clearly demonstrate the potential for low-power implementation of the proposed design.]]> 3 1 75 85 1716 3 1 86 95 1381 3 1 96 105 558 3 1 106 116 1764 3 1 117 117 104 3 1 118 118 112 3 1 119 120 1485 3 1 C3 C3 117