http://ieeexplore.ieee.org TOC Alert for Publication# 55 2012 February 10 33 2 C1 130 58 33 2 C2 C2 50 $(hbox{4F}^{2})$ cross-point memory arrays. The first prototype cells are demonstrated to operate with relatively low set/reset voltages and excellent retention characteristics and are multi-time programmable (with endurance exceeding $hbox{10}^{4}$ set/reset cycles).]]> 33 2 131 133 514 $S_{rm IF}/B_{rm mid}/D_{rm IF} = hbox{SiGe/SiGe/Si}$ as the interfacial source/middle body/interfacial drain. A large hysteresis window for the “read 1” from the “read 0” and a long retention time at low latch voltage could be also obtained.]]> 33 2 134 136 431 $N_{rm it}$ and electron oxide traps, localized near the drain. The on-state stress produced the negative bias temperature instability which generated $N_{rm it}$'s and positive oxide charges $Q_{rm ox}$ distributed uniformly in the channel. Although the electrons trapped by the off-state stress decreased the threshold voltage $vert V_{rm th}vert$, they were detrapped readily by the subsequent on-state stress. A dynamic stress caused the nanoscale pMOSFET to build up $N_{rm it}$ and positive $Q_{rm ox}$, which increased the $vert V_{rm th}vert$ significantly. These new observations indicate that the combined dynamic process can significantly influence the reliability of scaled CMOS inverter circuits.]]> 33 2 137 139 149 $I$– $V$ measurements on a $hbox{p}^{+}hbox{-}hbox{i}hbox{-} hbox{n}^{+}$ tunnel diode test structure fabricated on the same wafer as the TFET with common process steps. Assuming that doping concentration, Si thin-film thickness, and buried-oxide thickness are known from the fabrication process, this algorithm uses the maximum electric field extracted from the $I$–$V$ measurements and applies the analytical model to estimate the junction steepness. It has been observed that the estimations based on this method have a maximum deviation of sub-0.2 nm/decade from the actual junction steepness of the investigated devices.]]> 33 2 140 142 381 33 2 143 145 275 $kappa$ (HK) gate stack. Time-to-breakdown (BD) statistics for grain boundary (GB) and grain in a polycrystalline HK gate stack are obtained individually from localized constant voltage stressing via a scanning tunneling microscope. In spite of an initial difference in the preexisting defect density, no apparent difference in the Weibull slope is observed for the two sets of BD statistics. The bimodal Weibull distribution is shown to be a combined effect: 1) The steep Weibull slope of the lower percentile, arising from large-area devices, is related to BD at GBs, and 2) the upper percentile, arising from small-area devices, is mostly related to grain BDs. In this case, the Weibull slope is reduced by a small fraction of these devices exhibiting early failures due to GB BDs. We show directly that structural defects in an HK dielectric, particularly GBs, play an important role on its BD distribution.]]> 33 2 146 148 217 33 2 149 151 449 $( < hbox{5} hbox{pA}/muhbox{m})$ and high $I_{rm ON}/I_{rm OFF}$ ratio $(> hbox{10}^{6})$. Furthermore, we briefly discuss the implication of these devices in CMOS nand logic implementation.]]> 33 2 152 154 442 33 2 155 157 356 33 2 158 160 505 $hbox{8}F^{2}$ DRAM cell is introduced, consisting of two gates controlling a low-doped silicon-on-insulator channel and opposite-polarity source and drain. Simulation with models calibrated to experimental floating-body cell data confirms virtual thyristor memory operation and demonstrates 85 $^{circ}hbox{C}$ retention time in excess of 10 ms in a scaled FinFET architecture. With unit cell area comparable to that of conventional DRAM, 1.6-V total operation range, 1-ns program time, and CMOS-compatible process, floating-body diode is a candidate for stand-alone or embedded memory applications at 15-nm node and beyond.]]> 33 2 161 163 442 33 2 164 166 487 $<$ 0.5 V), due to its super-steep subthreshold slope $({SS}_{rm AVG} sim hbox{13} hbox{mV/dec}$ over six decades of current), ${I}_{rm ON}/{I}_{rm OFF}$ ratio of $simhbox{10}^{9}$, and drive current of ${I}_{rm ON} sim hbox{10} muhbox{A}/muhbox{m}$ at ${V}_{rm DD} = hbox{0.5} hbox{V}$. The same structure with symmetric voltages can be used to achieve a p-type device with ${I}_{rm ON}$ and ${I}_{rm OFF}$ levels comparable to the n-type, which enables a straightforward implementation of complementary logic that could theoretically reach a maximum operating frequency of 1.39 GHz when ${V}_{rm DD} = hbox{0.25} hbox{V}$.]]> 33 2 167 169 477 $(hbox{SiO}_{2}hbox{/Si}_{3}hbox{N}_{4}hbox{/SiO}_{2})$ with a high-$k$ $hbox{HfO}_{2}$ charge-trapping layer and an $hbox{Al}_{2}hbox{O}_{3}$ blocking layer was applied to TBE-TFT memory devices in order to enhance the memory performance of TBE-TFT memory devices. As a result, the poly-Si TFT charge-trap Flash memory with an engineered tunnel barrier exhibited excellent memory characteristics, such as large memory window (9.5 V), long retention time, and endurance.]]> 33 2 170 172 461 $sim$ 2.4%, biaxial) germanium-channel (7.8 nm-thick) p-MOSFETs with high-K/metal gate stack has been experimentally investigated. Devices with various ultrathin strained-Si cap layer thicknesses, as thin as $sim!! hbox{8} hbox{rm{AA}}$, show excellent capacitance-voltage characteristics with no hysteresis or frequency dispersion and hole mobility enhancement of more than 6.5X over Si universal and 2.3X over similar devices with no strained-Si cap, at $E_{rm eff} = hbox{0.6} hbox{MV/cm}$. The influence of the strained-Si cap thickness on the hole mobility is also studied. The mobility increases with increasing Si cap thickness up to $sim$1.8 nm (with a peak mobility of 940 $hbox{cm}^{2}/hbox{Vs}$ at this cap thickness) consistent with a reduction in remote Coulombic scattering.]]> 33 2 173 175 449 $(V_{t})$ fluctuations in high- $kappa$ gate dielectric and metal-gate pMOSFETs are investigated. We measured RTN amplitude distributions before and after NBT stress. RTN in poststressed devices exhibits a broader amplitude distribution than the prestress one. In addition, we trace a single trapped charge-induced $ Delta V_{t}$ in NBT stress and find that the average $Delta V_{t}$ is significantly larger than a $Delta V_{t}$ caused by RTN. A 3-D atomistic simulation is performed to compare a single-charge-induced $Delta V_{t}$ by RTN and NBTI. In our simulation, the probability distribution of a NBT trapped charge in the channel is calculated from the reaction-diffusion model. Our simulation confirms that the NBT-induced $Delta V_{t}$ indeed has a larger distribution tail than RTN due to a current-path percolation effect.]]> 33 2 176 178 290 $(C_{rm G})$ and read out through a fast feedback regeneration process. The simulated read/write times of our device reach below 1 ns, much faster than conventional 1T-1C DRAM. The read/write biasing voltages can be scaled down to 1.1 V, achieving long retention time $(t_{rm re} > hbox{5} hbox{s})$.]]> 33 2 179 181 401 $F_{rm MAX}$ above 400 GHz and thus has a growing interest for W-band applications. A load pull test bench is developed for the characterization of this device with special care on architecture and calibration procedure for accurate measurements in 75–110 GHz. The device was characterized under large signal operation showing attractive performance for power amplifier design. A state-of-the-art power density of 18.5 $hbox{mW}/muhbox{m}^{2}$ at 1-dB compression has been obtained at 94 GHz.]]> 33 2 182 184 488 $hbox{Si}:hbox{HfO}_{2}$ . The program and erase operation of this metal–ferroelectric–insulator–silicon FET (MFIS) with $hbox{poly-Si/TiN/Si}:hbox{HfO}_{2}hbox{/SiO}_{2}hbox{/Si}$ gate stack is compared to the transient switching behavior of a TiN-based metal–ferroelectric–metal (MFM) capacitor. Polarization reversal in the MFM capacitor follows a characteristic time and field dependence for ferroelectric domain switching, leading to a higher switching speed with increasing applied field. Similar observations were made for the material when implemented into an MFIS structure. Nonvolatile switching was observed down to 20-ns pulsewidth, yielding a memory window (MW) of 1.2 V. Further increase in gate bias or pulsewidth led to charge injection and degradation of the MW. Retention measurements for up to $hbox{10}^{6} hbox{s}$ suggest a retention of more than ten years.]]> 33 2 185 187 409 $k$ gate dielectric, the pMOSFET device with novel superlattice (SL) SiGe channels is proposed in this letter. Experimental results show that the electrical characteristics of MOSFET can be obviously improved by an SL virtual substrate. The peak hole mobility of the pMOSFET device with SL is enhanced by about 100% as compared to that with the Si one. The on–off ratio of the $Id{-}Vg$ curve is beyond eight orders, and the electrical thickness in inversion ($Tinv$) value of the gate dielectric can be $sim$1.4 nm. The source/drain activation temperature of 650 $^{circ}hbox{C}$ is particularly suitable to high- $k$ dielectric process.]]> 33 2 188 190 373 $k$ dielectrics is reported. Unlike the violation of weakest link failure property found in conventional TDDB evaluation with SILC interference, we have demonstrated that time-to-failure distributions obtained with this new methodology restores this universal property. Excellent results in terms of improved time to failure and Weibull slope were obtained, thus providing a realistic TDDB projection. The algorithm of this methodology is easy to implement and can be used in daily TDDB evaluation.]]> 33 2 191 193 510 $times$ 4.2 and $hbox{6.2} times hbox{6.2} hbox{nm}^{2}$. The average doping concentration is $hbox{10}^{20} hbox{cm}^{-3}$. The dopant distributions are randomly generated and modeled in a fully atomistic way. Phonon scattering, elastic and inelastic, is also included in the simulations. We show that junctionless nanowire transistors have a much higher subthreshold variability than their inversion mode counterparts for the equivalent geometry and doping level.]]> 33 2 194 196 370 $(N = hbox{2})$ and from 12 to 142 $(N = hbox{3})$ at $Vdd = hbox{0.5}{-}hbox{1} hbox{V}$. As the temperature increases or $Vdd$ decreases, the stack-effect factor for UTB GeOI devices decreases, while the stack-effect factor for bulk Ge-channel MOSFETs increases, because the subthreshold leakage current becomes more significant at higher temperature or lower voltage with respect to the band-to-band-tunneling leakage current.]]> 33 2 197 199 569 33 2 200 202 275 $hbox{SiO}_{2}$ pillar and anisotropic dry etching. Nanowire field-effect transistors (FETs), with channel lengths in the range of 1.3–18.6 $muhbox{m}$, are then fabricated using these 80 nm $ times$ 40 nm nanowires. Measured electrical results show n-type enhancement behavior and a breakdown voltage $geq$75 V at all channel lengths. This is the first report of high-voltage operation for ZnO nanowire FETs. Reproducible well-behaved electrical characteristics are obtained, and the drain current scales with $1/L$, as expected for long-channel FETs. A respectable $I_{rm ON}/I_{rm OFF}$ ratio of $hbox{2} times hbox{10}^{6}$ is obtained.]]> 33 2 203 205 157 $(NF_{min})$ at 94 GHz was improved effectively by employing a cavity structure in the interconnection process, even though a wide gate head was used in InP-based high-electron-mobility transistors (HEMTs). The wide gate head is effective in improving $NF_{min}$ since gate resistance is reduced, while increased parasitic capacitance at a passivated gate affects the noise figure. Then, the parasitic capacitance was eliminated successfully by employing a cavity structure around the gate region. We measured an $NF_{min}$ of 0.9 dB when the cavity structure was employed in the wide-gate-head HEMTs.]]> 33 2 206 208 344 $pm$ 0.9 dB from 7 to 11 GHz with a minimum noise figure of 1.4 dB at 9.8 GHz. The excellent LNA performance is enabled by the favorable characteristics of our InP HEMTs under low-power-dissipation biases. For example, at a bias of $V_{rm DS} = hbox{0.5 V}$ and $I_{rm DS} = hbox{66.2 mA/mm}$, our $(hbox{0.1} times hbox{2} times hbox{50} mu hbox{m}^{2})$ InP HEMTs feature cutoff frequencies of $f_{T} = hbox{183 GHz}$ and $f_{rm MAX} = hbox{230 GHz}$ . The present results demonstrate the excellent capabilities of InP-HEMT technology for high-speed, low-voltage, and room-temperature low-power-consumption applications.]]> 33 2 209 211 282 $hbox{Al}_{2}hbox{O}_{3}$ serving as both gate dielectric under the gate electrode and passivation layer in the access region was used. It was found that the $hbox{Al}_{2}hbox{O}_{3}$ was superior to $hbox{SiN}_{x}$ in increasing the 2-D electron gas (2DEG) density and thereby reducing the access resistance. In addition, the off -state leakage current $(I_{rm off})$ in these AlN/GaN MOSHFETs was reduced by four orders of magnitude to $hbox{7.6} times hbox{10}^{-5} hbox{mA/mm}$ as a result of the $hbox{Al}_{2} hbox{O}_{3}$ gate dielectric, compared to that of AlN/GaN HFETs. Meanwhile, the subthreshold slope was improved to a nearly ideal value of 62 mV/dec because of the extremely low $I_{rm off}$. The MOSHFETs with 1-$muhbox{m}$ gate length exhibited good DC characteristics. A maximum drain current of 745 mA/mm and a peak extrinsic transconductance of 280 mS/mm were achieved.]]> 33 2 212 214 380 $sim$190 mV/dec, and a high on/off current ratio $(I_{rm ON}/I_{rm OFF}) > hbox{10}^{6} (V_{D} = hbox{1} hbox{V})$ without hydrogen-related plasma treatments. After Ni salicidation, the devices exhibit steep SS $sim$ 148 mV/dec and $I_{rm ON}/I_{rm OFF} sim hbox{10}^{7}$. After $hbox{NH}_{3}$ plasma treatment, the characteristics of the devices are further improved. The LFin-TFTs have steeper SS $sim$ 132 mV/dec, higher $I_{ rm ON}/I_{rm OFF} > hbox{10}^{7}$, and threshold voltage $(V_{rm TH}) sim hbox{0.036} hbox{V}$.]]> 33 2 215 217 489 $V_{rm th}$ shift toward negative direction, as reported in previous works. However, the trapping probability of a single hole is not altered, which means that the basic mechanism of the charge trapping is not changed by light illumination. In oxide TFTs, the hole concentration at the channel and the characteristics of the gate insulator materials are the determinant factors of the reliability under light illumination.]]> 33 2 218 220 307 $hbox{SiO}_{2}$ cladding, were fabricated simultaneously with Cu TSVs. The characteristics of light confinement of the TSPV were measured using a near-field pattern measurement. The spot light area was well confined within the TSPV without interference from the lights. The optical intensity that passed through the TSPV was 20% higher than that which passed through the Si substrate. The unidirectional optical coupler with two mirrors showed higher coupling efficiency. Laser light can be efficiently propagated to a planar Si waveguide through the TSPV and the unidirectional coupler.]]> 33 2 221 223 496 33 2 224 226 414 33 2 227 229 263 33 2 230 232 525 $muhbox{W}$ of external electric power. The new technology also opens the path to a new generation of sensors and microsystems embedded in metals during primary shaping.]]> 33 2 233 235 304 $hbox{Pt}/hbox{NbO}_{2}/hbox{Pt}$ device with a memory-switching (MS) $hbox{Pt}/hbox{Nb}_{2}hbox{O}_{5}/ hbox{Pt}$ device and observe the suppression of the undesired sneak current. A simpler $hbox{Pt}/hbox{Nb}_{2}hbox{O}_{5}/hbox{NbO}_{2}/hbox{Pt}$ bilayer oxide device was designed; it simultaneously exhibits TS and MS. The unique device characteristics in the metal/oxide/metal structure can be directly integrated into a crosspoint memory array without the diode; this can significantly reduce the fabrication complexity.]]> 33 2 236 238 434 33 2 239 241 403 $ hbox{SiH}_{4}$ ramp-up ambient in a conventional batch-type furnace in order to minimize the growth of native oxide. A deposition/etch-back/deposition scheme enabled us to achieve robust vertical diodes without any seams or interfacial oxide layer within the vertical diode pillars. Subsequent annealing at 600 $^{circ}hbox{C}$ provided solid-phase epitaxial alignment of the a-Si layer. An ideality factor revealed that the new scheme provided noticeable crystallinity of the silicon diodes. Moreover, the electrical characteristics of the diodes verified that the scheme was suitable for full operation of PCM devices.]]> 33 2 242 244 360 33 2 245 247 338 33 2 248 250 249 $I$. The $hbox{1}/f^{gamma}$ noise with $gamma sim hbox{1.3}$ (for low $I$) or 0.6 (for high $I$ ) was observed to dominate the LFN, and the noise power spectral density $S_{i}$ showed a power-law behavior ($S_{i} sim I^{alpha}$ , where $alpha sim hbox{2}$). This quadratic behavior may indicate the $hbox{1}/f^{gamma}$ noise to stem from the carrier number fluctuations mediated by deep trap states (for $gamma sim hbox{1.3}$) or band tail states (for $gamma sim hbox{0.6}$) of nc-Si:H. Also, the band tail width of nc-Si:H was estimated to be $sim$65 meV.]]> 33 2 251 253 314 33 2 254 256 382 $hbox{Ag/GeS}_{2}/hbox{W}$ conductive-bridge random access memory (CBRAM) cells are shown to program at room temperature to conductance levels near multiples of the fundamental conductance $G_{0} = hbox{2}e^{2}/h$. This behavior is not accounted for in the traditional view that the conductance of a CBRAM cell is a continuous variable proportional to the maximum current allowed to flow during programming. For on -state resistances on the order of $hbox{1}/G_{0} = hbox{12.9} hbox{k}Omega$ or less, quantization implies that the Ag “conductive bridge” typically contains a constriction, or even an extended chain, that can be as narrow as a single atom. Implications for device modeling and commercial applications are discussed.]]> 33 2 257 259 260 33 2 260 262 348 $(f_{T})$ of 630 kHz. In addition to the cutoff frequency, other important figures of merit for the RF transistor are also presented, including the common-emitter current gain and on/off ratio.]]> 33 2 263 265 351 33 2 266 268 459 33 2 269 271 535 $muhbox{m}$-1-poly-6-metal foundry CMOS technology have been demonstrated for the first time to substantially improve their electromechanical coupling coefficient, hence leading to a motional impedance of only 880 $hbox{k}Omega$ at 15.3 MHz. A simple maskless wet release process has been successfully transferred from a 0.35- $muhbox{m}$ platform to an advanced 0.18-$muhbox{m}$ version, capable of offering enhanced gap spacing and transduction area for CMOS–MEMS resonators monolithically integrated with high-performance CMOS circuitry. This proposed platform offers ease of use, fast turnaround time, low cost, convenient prototyping, and inherent MEMS-circuit integration, therefore showing great potential toward future integrated sensing and single-chip RF applications.]]> 33 2 272 274 515 $ hbox{44} muhbox{m} times hbox{27} muhbox{m}$ and a V-groove cavity of $hbox{48} muhbox{m} times hbox{45} muhbox{m}$ were estimated as 4.37 and 4.24 $muhbox{m}$ by the respective calculations based on the simulation and measurement results which are much lower than those calculated by early models of published papers. The gas conductance of the sensor in atmosphere was further evaluated as $hbox{1.4} times hbox{10}^{-5} hbox{W/K}$ which dominates the heat loss of the thermal sensor.]]> 33 2 275 277 116 33 2 278 280 304 33 2 281 283 634 $( Delta V)$, sensitivity, and signal-to-noise ratio of the 3-D microheater-based gas sensor were more than twice of those of the 2-D microheater-based gas sensor. Moreover, it had a higher output signal-to-power ratio $(Delta hbox{V/P})$.]]> 33 2 284 286 423 33 2 287 288 59 33 2 289 289 29 33 2 290 290 118 33 2 291 C3 61 33 2 C4 C4 5