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		<title><![CDATA[ Electron Device Letters, IEEE - new TOC ]]></title>
		<link>http://ieeexplore.ieee.org</link>
		<description>TOC Alert for Publication# 55 </description>
		<year>2013</year>
		<month>May      </month>
		<day>16</day>
		<item>
			<title><![CDATA[Table of contents]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6507367]]></link>
			<description><![CDATA[Presents the cover/table of contents for this issue of the periodical.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6507367]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>C1</startPage>
			<endPage>574</endPage>
			<fileSize>166</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Electron Device Letters publication information]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6506863]]></link>
			<description><![CDATA[Provides a listing of current committee members and society officers.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6506863]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>C2</startPage>
			<endPage>C2</endPage>
			<fileSize>149</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[Plasma Damage Mechanism of Electron Beam Curing Process for Spin on Dielectrics]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6490006]]></link>
			<description><![CDATA[This letter presents the plasma damage mechanism of electron beam curing process for spin on dielectrics. Device damage is studied using the antenna gate metal-oxide-semiconductor field-effect transistor (MOSFET) in terms of the threshold voltage variation as a function of electron beam conditions such as ambient and cathode voltage. Threshold voltages of nMOSFET are decreased by an electron beam curing process without antenna ratio dependency. The electron energy and interlayer dielectric thickness between active devices and metal layers largely affect the variation of threshold voltage. From the experimental results, it is concluded that device damage induced by an electron beam curing process is characterized as radiation damage rather than electron charging damage. For the damage free electron beam curing process, it is essential to control the penetration depth of high-energy electrons by adjusting the cathode voltage while considering the dielectric thickness over active devices.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6490006]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>575</startPage>
			<endPage>577</endPage>
			<fileSize>274</fileSize>
			<authors><![CDATA[Sung Gyu Pyo;Sibum Kim;]]></authors>
		</item>
		<item>
			<title><![CDATA[Impact of Using Double-Patterning Versus Single-Patterning on Threshold Voltage <formula formulatype="inline"> <img src="/images/tex/20892.gif" alt="(V_{\rm TH})"> </formula> Variation in Quasi-Planar Tri-Gate Bulk MOSFETs]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6484101]]></link>
			<description><![CDATA[To experimentally investigate the impact of double-patterning and double-etching (2P2E) versus single-patterning and single-etching (1P1E) on the line-edge-roughness (LER) as well as on the LER-induced threshold-voltage (<i>V</i><sub>TH</sub>) variation in a multigate bulk device, quasi-planar tri-gate (QPT) bulk metal-oxide semiconductor field-effect transistors (MOSFETs) are fabricated by a 28-nm complementary metal-oxide-semiconductor (CMOS) technology. It is experimentally verified that the LER profile obtained through using the 2P2E 193-nm immersion photolithography technique has a relatively longer correlation length (i.e., lower spatial frequency) than that by the 1P1E technique, although they have a comparable root-mean-square deviation and fractal dimension. By using Monte Carlo simulations to analyze the random <i>V</i><sub>TH</sub> variations in the QPT bulk MOSFETs, we confirm that the 2P2E-LER-induced <i>V</i><sub>TH</sub> variation (versus the 1P1E-LER-induced <i>V</i><sub>TH</sub> variation) is suppressed by ~20% in terms of &#x03C3;(<i>V</i><sub>TH</sub>). However, the total <i>V</i><sub>TH</sub> variation in the QPT MOSFETs is slightly improved with the 2P2E technique, because the other variation sources such as random dopant fluctuation and work-function variation have still dominated the total <i>V</i><sub>TH</sub> variation. To fully benefit from the 2P2E technique, the other random/intrinsic variations should be better controlled in the QPT CMOS technology.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6484101]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>578</startPage>
			<endPage>580</endPage>
			<fileSize>413</fileSize>
			<authors><![CDATA[Changhwan Shin;In Jun Park;]]></authors>
		</item>
		<item>
			<title><![CDATA[Low-Temperature Quantum Transport Characteristics in Single n-Channel Junctionless Nanowire Transistors]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6480784]]></link>
			<description><![CDATA[A single n-channel junctionless nanowire transistor is fabricated and characterized for low-temperature quantum transport behavior. Transfer characteristics exhibit current oscillations below flat-band voltage (<i>V</i><sub>FB</sub>) up to temperature 75 K, possibly due to cotunneling through unintentional quantum dots. Furthermore, regular current steps are observed above <i>V</i><sub>FB</sub>, that is, each current plateau corresponds to a fully populated subband. Experimental result of transconductance peaks indicates that the subband energy spacing in the 1-D channel agrees well with theoretical prediction.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6480784]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>581</startPage>
			<endPage>583</endPage>
			<fileSize>396</fileSize>
			<authors><![CDATA[Xiaoming Li;Weihua Han;Liuhong Ma;Hao Wang;Yanbo Zhang;Fuhua Yang;]]></authors>
		</item>
		<item>
			<title><![CDATA[Junctionless Tunnel Field Effect Transistor]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6497488]]></link>
			<description><![CDATA[In this letter, a double-gate junctionless tunnel field effect transistor (JL-TFET) is proposed and investigated. The JL-TFET is a Si-channel heavily n-type-doped junctionless field effect transistor (JLFET), which uses two isolated gates (Control-Gate, P-Gate) with two different metal work-functions to behave like a tunnel field effect transistor (TFET). In this structure, the advantages of JLFET and TFET are combined together. The simulation results of JL-TFET with high-k dielectric material (TiO2) of 20-nm gate length shows excellent characteristics with high I<sub>ON</sub>/I<sub>OFF</sub> ratio (~6&#x00D7;10<sup>8</sup>), a point subthreshold slope (SS) of ~38 mV/decade, and an average SS of ~70 mV/decade at room temperature, which indicates that JL-TFET is a promising candidate for a switching performance.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6497488]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>584</startPage>
			<endPage>586</endPage>
			<fileSize>704</fileSize>
			<authors><![CDATA[Ghosh, B.;Akram, M.W.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Performance Enhancement on p-Channel Charge-Trapping Flash Memory Device With Epitaxial Si/Ge Super-Lattice Channel]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6479681]]></link>
			<description><![CDATA[Operation characteristics of p-channel <formula formulatype="inline"><tex Notation="TeX">${rm TaN}/{rm Al}_{2}{rm O}_{3}/{rm HfO}_{2}/{rm HfAlO}_{2}/{rm SiO}_{2}/{rm Si}$</tex></formula> MAHOS-type nonvolatile memory devices with an epitaxial Si/Ge super-lattice (SL) channel are investigated in this letter, where the SL channel is characterized with good crystal structure and high thermal stability. Remarkable improvement on programming and erasing speeds is observed, as compared to those with SiGe channel. Furthermore, the degradation on reliability properties of retention and endurance is negligible for the device with employing a SL channel.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6479681]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>587</startPage>
			<endPage>589</endPage>
			<fileSize>303</fileSize>
			<authors><![CDATA[Liu, L.-J.;Chang-Liao, K.-S.;Jian, Y.-C.;Cheng, J.-W.;Wang, T.-K.;Tsai, M.-J.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Switchable Electric Field Induced Diode Effect in Nanostructured Porous Silicon]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502196]]></link>
			<description><![CDATA[Unidirectional current flow (diode-like behavior) is observed in Al/Nanostructured Porous Silicon/Al structures (Al/SP/Al) after applying a forming electric field (<i>E</i>) for a long time. We found that rectifying characteristics depend on the direction of <i>E</i>. The forward direction coincides with the direction of <i>E</i>. The diode direction switches when <i>E</i> is inverted. The rectification factor passes from 200 to 26 from one direction to the other, the effect is reversible and can be repeated several times.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502196]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>590</startPage>
			<endPage>592</endPage>
			<fileSize>542</fileSize>
			<authors><![CDATA[Marin, O.;Urteaga, R.;Comedi, D.;Koropecki, R.R.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Improved NBTI Reliability With Sub-1-Nanometer EOT <formula formulatype="inline">  <img src="/images/tex/20231.gif" alt="{\rm ZrO}_{2}"> </formula> Gate Dielectric Compared With <formula formulatype="inline"> <img src="/images/tex/681.gif" alt="{\rm HfO}_{2}"> </formula>]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502193]]></link>
			<description><![CDATA[The negative bias temperature instability (NBTI) reliability of sub-1-nanometer equivalent oxide thickness (EOT) ZrO<sub>2</sub> and HfO<sub>2</sub> dielectrics with metal gate is investigated. The threshold voltage shift (&#x0394;<i>V</i><sub>TH</sub>) at identical NBTI over-drive stress conditions is observed to be lower in ZrO<sub>2</sub> than in HfO<sub>2</sub> field-effect transistors. Ring oscillator charge pumping is applied to determine interface trap generation (&#x0394;<i>N</i><sub>it</sub>) in the sub-1-nanometer EOT devices, with ZrO<sub>2</sub> devices showing about one order of magnitude lower &#x0394;<i>N</i><sub>it</sub> than HfO<sub>2</sub> device. However, the &#x0394;<i>N</i><sub>it</sub> contribution to the total &#x0394;<i>V</i><sub>TH</sub> is very limited in sub-1-nanometer EOT devices, as the recoverable component from the pre-existing bulk defects dominates the whole NBTI degradation. Pulsed Id-Vg technique is applied to analyze the pre-existing bulk defects in those sub-1-nanometer EOT devices, and lower pre-existing bulk defect density is shown in ZrO<sub>2</sub>, which decisively reduces NBTI in ZrO<sub>2</sub> gate dielectric.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502193]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>593</startPage>
			<endPage>595</endPage>
			<fileSize>477</fileSize>
			<authors><![CDATA[Moonju Cho;Kaczer, B.;Kauerauf, T.;Ragnarsson, L.-A.;Groeseneken, G.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Morphology and Electrical Performance Improvement of NiGe/Ge Contact by P and Sb Co-implantation]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6490005]]></link>
			<description><![CDATA[In this letter, co-implantation of P and Sb dopants into NiGe film is first proposed to improve the characteristic of NiGe/Ge contact. Through this technique, obvious enhancement of NiGe thermal stability is achieved. The surface morphology of NiGe film even keeps smooth and flat after post-germanidation annealing up to 600&#x00B0;C. The current characteristics of the formed NiGe/p-Ge diodes are also improved, exhibiting better rectifying performance. It is believed that the improved interface quality and the enhanced dopant activation contribute to these improvements. Therefore, this technique shows great potential for high performance Ge device technology.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6490005]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>596</startPage>
			<endPage>598</endPage>
			<fileSize>1535</fileSize>
			<authors><![CDATA[Zhiqiang Li;Xia An;Min Li;Quanxin Yun;Meng Lin;Ming Li;Xing Zhang;Ru Huang;]]></authors>
		</item>
		<item>
			<title><![CDATA[Hydrazine-Based Fermi-Level Depinning Process on Metal/Germanium Schottky Junction]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502197]]></link>
			<description><![CDATA[In this letter, we propose a hydrazine (N<sub>2</sub>H<sub>4</sub>)-based nitridation process, which reduces the native oxide (GeO<sub>x</sub>) component and finally transforms it into GeO<sub>x</sub>N<sub>y</sub> on intrinsic Ge, to relieve the E<sub>F</sub> pinning problem. The decomposition of GeO<sub>x</sub> and formation of GeO<sub>x</sub>N<sub>y</sub> by N<sub>2</sub>H<sub>4</sub> are systematically investigated through cross-sectional transmission electron microscopy, X-ray photoelectron spectroscopy, and atomic force microscopy analyses. After performing the N<sub>2</sub>H<sub>4</sub>-based nitridation process for 12 h, high &#x03A6;<sub>H</sub> (~0.59 eV) and therefore high ON/OFF current ratio (~10<sup>4</sup>) are achieved for Ti/Ge Schottky junction diode.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502197]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>599</startPage>
			<endPage>601</endPage>
			<fileSize>508</fileSize>
			<authors><![CDATA[Hyun-Wook Jung;Woo-Shik Jung;Jin-Hong Park;]]></authors>
		</item>
		<item>
			<title><![CDATA[Emitter Size Effect in GaAsSb-Based DHBTs With AlInP and GaInP Emitters]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6491438]]></link>
			<description><![CDATA[Recombination effects in GaAsSb-based double-heterojunction bipolar transistors featuring AlInP and GaInP emitters are investigated. AlInP emitters provide a reduced intrinsic recombination but result in a significantly increased base surface recombination in comparison to GaInP emitters. Photoluminescence measurements confirm that the GaAsSb surface after etching AlInP has a higher recombination velocity and exhibits a greater sensitivity to the passivation method than when a GaInP emitter is used.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6491438]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>602</startPage>
			<endPage>604</endPage>
			<fileSize>385</fileSize>
			<authors><![CDATA[Lovblom, R.;Fluckiger, R.;Ostinelli, O.;Alexandrova, M.;Bolognesi, C.R.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Source-Connected p-GaN Gate HEMTs for Increased Threshold Voltage]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6479233]]></link>
			<description><![CDATA[A pathway to increase the threshold voltage (<i>V</i><sub>TH</sub>) of p-GaN gate high-electron-mobility transistors (HEMTs) is presented. The hole depletion width in the p-GaN layer at the gate interface is one of the key controlling factors of <i>V</i><sub>TH</sub> in p-GaN gate HEMTs. In order to increase the depletion width, we devise a new device structure of p-GaN gate HEMT having a source-connected p-GaN bridge. We demonstrate that a bridged p-GaN gate HEMT structure increases the <i>V</i><sub>TH</sub> from 0.93 to 2.44 V.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6479233]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>605</startPage>
			<endPage>607</endPage>
			<fileSize>499</fileSize>
			<authors><![CDATA[Injun Hwang;Jaejoon Oh;Hyuk Soon Choi;Jongseob Kim;Hyoji Choi;Joonyong Kim;Soogine Chong;Jaikwang Shin;U-In Chung;]]></authors>
		</item>
		<item>
			<title><![CDATA[Variability Improvement by Interface Passivation and EOT Scaling of InGaAs Nanowire MOSFETs]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6475962]]></link>
			<description><![CDATA[High-performance InGaAs gate-all-around (GAA) nanowire MOSFETs with channel length (<i>L</i><sub>ch</sub>) down to 20 nm are fabricated by integrating a higher <i>k</i> LaAlO<sub>3</sub>-based gate-stack with an equivalent oxide thickness of 1.2 nm. It is found that inserting an ultrathin (0.5 nm) Al<sub>2</sub>O<sub>3</sub> interfacial layer between the higher <i>k</i> LaAlO<sub>3</sub> and InGaAs can significantly improve the interface quality and reduce device variation. As a result, a record low subthreshold swing of 63 mV/dec is demonstrated at sub-80-nm <i>L</i><sub>ch</sub> for the first time, making InGaAs GAA nanowire devices a strong candidate for future low-power transistors.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6475962]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>608</startPage>
			<endPage>610</endPage>
			<fileSize>1141</fileSize>
			<authors><![CDATA[Gu, J.J.;Xinwei Wang;Heng Wu;Gordon, R.G.;Ye, P.D.;]]></authors>
		</item>
		<item>
			<title><![CDATA[High-Speed GaN-Based Blue Light-Emitting Diodes With Gallium-Doped ZnO Current Spreading Layer]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6490009]]></link>
			<description><![CDATA[Conventional light-emitting diodes (LEDs) always pursue the high brightness required for solid-state lighting. However, they always exhibit very low frequency bandwidth of tens MHz. In this letter, we investigate the fabrication and characterization of high-speed GaN-based blue LEDs. The frequency response of LEDs is mainly limited by its diffusion capacitance and resistance, and the injected carriers in the active region of the device. Through appropriate device design, gallium-doped Zinc oxide film deposited by atomic layer deposition is used as the top contact layer with high lateral resistance to self-confine the current injection. In addition, a smaller bonding pad is used to reduce the RC time constant. Thus, the GaN-based blue LEDs with a 75-<formula formulatype="inline"><tex Notation="TeX">$mu{rm m}$</tex> </formula> diameter exhibit a 3-dB modulation bandwidth of 225.4 MHz and a light output power of 1.6 mW at the current of 35 mA. Such LEDs can be applied to visible light communication in future.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6490009]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>611</startPage>
			<endPage>613</endPage>
			<fileSize>467</fileSize>
			<authors><![CDATA[Liao, C.-L.;Chang, Y.-F.;Ho, C.-L.;Wu, M.-C.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Modeling the Impact of Reset Depth on Vacancy-Induced Filament Perturbations in <formula formulatype="inline"> <img src="/images/tex/681.gif" alt="{\rm HfO}_{2}"> </formula> RRAM]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502198]]></link>
			<description><![CDATA[Random telegraph noise in resistive switching memory devices is governed by two distinct mechanisms-oxygen vacancy perturbations in the filament as well as the electron trapping-detrapping phenomenon. In this letter, we focus on the dominant role of vacancies in governing the stability of the filament in the high resistance state and characterize the dependence of the read disturb voltage (<i>V</i><sub>DIST</sub>) on the depth of the reset level during switching. Our slow voltage ramp read disturb tests at different reset levels indicate the possibility of filamentary instability even for read voltages lower than the standard value of 0.10 V. These experimental trends can be well explained using the quantum point contact model for conduction in the filament, as deeper reset levels induce very steep potential gradients at the two ends of the constriction that make the filaments highly unstable and susceptible to structural modifications due to vacancy generation and/or transport during memory read operation.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502198]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>614</startPage>
			<endPage>616</endPage>
			<fileSize>558</fileSize>
			<authors><![CDATA[Raghavan, N.;Degraeve, R.;Fantini, A.;Goux, L.;Wouters, D.J.;Groeseneken, G.;Jurczak, M.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Hopping Effect of Hydrogen-Doped Silicon Oxide Insert RRAM by Supercritical <formula formulatype="inline"> <img src="/images/tex/802.gif" alt="{\rm CO}_{2}"> </formula> Fluid Treatment]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6493386]]></link>
			<description><![CDATA[In this letter, we introduced hydrogen ions into titanium metal doped into SiO<sub>2</sub> thin film as the insulator of resistive random access memory (RRAM) by supercritical carbon dioxide (SCCO)<sub>2</sub> fluid treatment. After treatment, low resistance state split in to two states, we find the insert RRAM, which means it has an operating polarity opposite from normal RRAM. The difference of the insert RRAM is owing to the resistive switching dominated by hydrogen ions, dissociated from OH bond, which was not by oxygen ions as usual. The current conduction mechanism of insert RRAM was hopping conduction due to the metal titanium reduction reaction through SCCO<sub>2</sub>.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6493386]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>617</startPage>
			<endPage>619</endPage>
			<fileSize>553</fileSize>
			<authors><![CDATA[Kuan-Chang Chang;Chih-Hung Pan;Ting-Chang Chang;Tsung-Ming Tsai;Rui Zhang;Jen-Chung Lou;Tai-Fa Young;Jung-Hui Chen;Chih-Cheng Shih;Tian-Jian Chu;Jian-Yu Chen;Yu-Ting Su;Jhao-Ping Jiang;Kai-Huang Chen;Hui-Chun Huang;Yong-En Syu;Der-Shin Gan;Sze, S.M.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Reliability Comparison of ISSG Oxide and HTO as Tunnel Dielectric in 3-D&#x2013;SONOS Applications]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6504710]]></link>
			<description><![CDATA[The reliability (endurance and retention) of tunnel oxide (grown and deposited oxide) of 3-D-SONOS devices is compared. Devices with grown tunnel oxide show better initial oxide quality, better fresh retention, and more robust endurance characteristics. Both devices show similar cycling degradation trend. The worse postcycling retention is due to tunnel oxide degradation leading to a fast initial loss of charge stored in generated tunnel oxide defects and a higher trap-assisted tunneling rate.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6504710]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>620</startPage>
			<endPage>622</endPage>
			<fileSize>329</fileSize>
			<authors><![CDATA[Fengying Qiao;Arreghini, A.;Blomme, P.;Date, L.;Van den bosch, G.;Liyang Pan;Jun Xu;Van Houdt, J.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Cycle-to-Cycle Intrinsic RESET Statistics in <formula formulatype="inline"> <img src="/images/tex/681.gif" alt="{\rm HfO}_{2}"> </formula>-Based Unipolar RRAM Devices]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6493387]]></link>
			<description><![CDATA[The statistics of the RESET voltage <formula formulatype="inline"><tex Notation="TeX">$(V_{rm RESET})$</tex></formula> and the RESET current <formula formulatype="inline"><tex Notation="TeX">$(I_{rm RESET})$</tex></formula> of <formula formulatype="inline"><tex Notation="TeX">${rm Pt}/{rm HfO}_{2}/{rm Pt}$</tex></formula> resistive random access memory (RRAM) devices operated under unipolar mode are analyzed. The experimental results show that both the distributions of <formula formulatype="inline"><tex Notation="TeX">$I_{rm RESET}$</tex></formula> and <formula formulatype="inline"><tex Notation="TeX">$V_{rm RESET}$</tex></formula> are strongly influenced by the distribution of initial resistance in the ON state <formula formulatype="inline"><tex Notation="TeX">$(R_{rm ON})$</tex></formula>, which is related to the size of the conductive filament (CF) before RESET. By screening the statistical data into different resistance ranges, both the distributions of <formula formulatype="inline"><tex Notation="TeX">$I_{rm RESET}$</tex></formula> and <formula formulatype="inline"><tex Notation="TeX">$V_{rm RESET}$</tex></formula> are shown to be compatible with a Weibull model. Contrary to previous reports for NiO-based RRAM, the Weibull slopes of the <formula formulatype="inline"><tex Notation="TeX">$I_{rm RESET}$</tex></formula> and <formula formulatype="inline"><tex Notation="TeX">$V_{rm RESET}$</tex></formula> are demonstrated to be independent of <formula formulatype="inline"><tex Notation="TeX">$R_{rm ON}$</tex></formula>. This is an indication that the RESET point, defined in this letter as the point of maximum current, corresponds to the initial phase of CF dissolution. On the other hand, given that the scale factor of the <formula formulatype="inline"><tex Notation="TeX">$V_{rm RESET}$</tex></formula> distribution <formula formulatype="inline"><tex Notation="TeX">$(V_{rm RESET63%})$</tex></formula> is roughly independent of <formula formulatype="inli-
e"><tex Notation="TeX">$R_{rm ON}$</tex></formula>, the scale factor of the <formula formulatype="inline"> <tex Notation="TeX">$I_{rm RESET}$</tex></formula> <formula formulatype="inline"><tex Notation="TeX">$(I_{rm RESET63%})$</tex></formula> is inversely proportional to <formula formulatype="inline"><tex Notation="TeX">$R_{rm ON}$</tex></formula>. This is analogous to what was found in NiO-based RRAM and it is consistent with the thermal dissolution model of RESET. Our results highlight the intrinsic link between the SET and RESET statistics and the need for controlling the variation of ON-state resistance to reduce the variability of the RESET voltage and current.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6493387]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>623</startPage>
			<endPage>625</endPage>
			<fileSize>601</fileSize>
			<authors><![CDATA[Long, S.;Lian, X.;Ye, T.;Cagli, C.;Perniola, L.;Miranda, E.;Liu, M.;Sune, J.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Postcycling LRS Retention Analysis in <formula formulatype="inline"> <img src="/images/tex/20893.gif" alt="{\rm HfO}_{2}/{\rm Hf}"> </formula> RRAM 1T1R Device]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6490333]]></link>
			<description><![CDATA[Low resistance state (LRS) retention after 10<sup>4</sup> and 10<sup>6</sup> pulse cycles is compared to the uncycled LRS retention, based on the (40 &#x00D7; 40 nm)- HfO<sub>2</sub>/Hf bipolar RRAM devices in a 1T1R configuration. The LRS retention after 10<sup>4</sup> pulse cycles does not show degradation, while a larger failure bit tail is seen after 10<sup>6</sup> pulse cycles. The larger failure bit tail is found strongly related to the degradation of the cycled LRS state. From the LRS current fitting with a quantum point contact model, it is found that the total number of oxygen vacancies (V<sub>ox</sub>) in the filament decreases after 10<sup>6</sup> cycles, leaving a narrower switching constriction. The narrower switching constriction therefore suffers more from the self-diffusion of the (V<sub>ox</sub>)'s from the filament into HfO<sub>2</sub> bulk, and results in degradation of the LRS retention.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6490333]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>626</startPage>
			<endPage>628</endPage>
			<fileSize>695</fileSize>
			<authors><![CDATA[Yang Yin Chen;Degraeve, R.;Govoreanu, B.;Clima, S.;Goux, L.;Fantini, A.;Kar, G.S.;Wouters, D.J.;Groeseneken, G.;Jurczak, M.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Dynamic Analysis of Current-Voltage Characteristics of Nanoscale Gated-Thyristors]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6497489]]></link>
			<description><![CDATA[This letter presents a detailed experimental investigation of the current-voltage characteristics of deca-nanometer gated-thyristors, highlighting that strong differences exist between the static and the dynamic operation of these devices. In particular, results reveal that the forward-breakover voltage determining thyristor turn-on does not depend only on the applied gate voltage, but also on the rise time of the applied gate pulse, decreasing for fast pulse fronts. This is explained in terms of a higher electron injection from the cathode to the anode triggering device turn-on when the gate switching time is shorter than that required for holes to leave the p-base.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6497489]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>629</startPage>
			<endPage>631</endPage>
			<fileSize>286</fileSize>
			<authors><![CDATA[Paolucci, G.M.;Compagnoni, C.M.;Castellani, N.;Carnevale, G.;Fantini, P.;Ventrice, D.;Lacaita, A.L.;Spinelli, A.S.;Benvenuti, A.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Impact of Charge Trapping Layer Thickness and New Trade-Off in Performance Characteristics of 3-D SONOS Devices]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6504469]]></link>
			<description><![CDATA[We evaluate the impact of silicon nitride (SiN) layer thickness in BiCS-like 3-D SONOS devices via standard and advanced characterization techniques, based on program (erase) efficiency measurements. SiN thickness below 4 nm strongly impacts electron trapping efficiency, resulting in degraded program operation but enhanced erase saturation level and hence giving rise to a new program-erase trade-off. An optimal 4 nm SiN thickness is assessed for proper MLC operation.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6504469]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>632</startPage>
			<endPage>634</endPage>
			<fileSize>263</fileSize>
			<authors><![CDATA[Arreghini, A.;Kar, G.S.;Van den bosch, G.;Van Houdt, J.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Two-Step Electrical Degradation Behavior in <formula formulatype="inline">  <img src="/images/tex/451.gif" alt="\alpha "> </formula>-InGaZnO Thin-Film Transistor Under Gate-Bias Stress]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6479236]]></link>
			<description><![CDATA[Investigated transfer characteristics on threshold voltage instability behavior in amorphous indium-gallium-zinc oxide thin-film transistor (&#x03B1;-IGZO TFT). A two-step electrical degradation behavior of &#x03B1;-IGZO TFT was found under gate-bias stress. A usual small positive shift followed by a special negative shift of threshold voltage is characterized in the &#x03B1;-IGZO TFT device. We suggest that the positive shift of the threshold voltage is due to the charge trapping in the gate dielectric and/or at the channel/dielectric interface, while the negative shift of threshold voltage is assigned to electric field-induced extra electron carriers from H<sub>2</sub>O molecules in the back channel protective layer. We conclude that the H<sub>2</sub>O molecules and the quality of passivation layer affect the degradation behavior of &#x03B1;-IGZO TFT devices.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6479236]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>635</startPage>
			<endPage>637</endPage>
			<fileSize>696</fileSize>
			<authors><![CDATA[Fa-Hsyang Chen;Tung-Ming Pan;Ching-Hung Chen;Jiang-Hung Liu;Wu-Hsiung Lin;Po-Hsueh Chen;]]></authors>
		</item>
		<item>
			<title><![CDATA[Hot-Carrier Effect on Amorphous In-Ga-Zn-O Thin-Film Transistors With a Via-Contact Structure]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6479680]]></link>
			<description><![CDATA[The effect of hot carriers on the characteristics of via-contact-type amorphous In-Ga-Zn-O thin-film transistors is investigated. After hot-carrier stress, the gate-to-source capacitance curve shows a two-stage rise while the gate-to-drain capacitance curve exhibits parallel shifts. It is found that hot electrons are injected into the etch-stop layer or trapped at the InGaZnO/etch-stop layer interface below redundant drain electrode. This is further verified by measuring the characteristic capacitance curve with a positive top gate bias.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6479680]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>638</startPage>
			<endPage>640</endPage>
			<fileSize>403</fileSize>
			<authors><![CDATA[Tien-Yu Hsieh;Ting-Chang Chang;Yu-Te Chen;Po-Yung Liao;Te-Chih Chen;Ming-Yen Tsai;Yu-Chun Chen;Bo-Wei Chen;Ann-Kuo Chu;Cheng-Hsu Chou;Wang-Cheng Chung;Jung-Fang Chang;]]></authors>
		</item>
		<item>
			<title><![CDATA[Unified Subthreshold Coupling Factor Technique for Surface Potential and Subgap Density-of-States in Amorphous Thin Film Transistors]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6479234]]></link>
			<description><![CDATA[We report a unified subthreshold coupling factor technique for a simultaneous extraction of the surface potential (&#x03C8;<sub>S</sub>) and the subgap density-of-states [DOS: g(E)] over the bandgap in amorphous semiconductor thin film transistors (TFTs). It is fully based on the experimental gate bias-dependent coupling factor [m(V<sub>GS</sub>)] under subthreshold bias. Through the proposed technique only with current-voltage data under subthreshold operation, a unified extraction of the DOS with a consistent mapping of the gate bias (V<sub>GS</sub>) to the subgap energy is obtained. Applying to amorphous InGaZnO TFTs, g(E) is obtained to be a superposition of two exponential functions with N<sub>TA</sub> = 1.62 &#x00D7; 10<sup>17</sup> eV<sup>-1</sup> cm<sup>-3</sup> and kT<sub>TA</sub> = 0.026 eV for the tail states while N<sub>DA</sub> = 6.5 &#x00D7; 10<sup>16</sup> eV<sup>-1</sup> cm<sup>-3</sup> and kT<sub>DA</sub> = 0.22 eV for the deep states.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6479234]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>641</startPage>
			<endPage>643</endPage>
			<fileSize>495</fileSize>
			<authors><![CDATA[Sungwoo Jun;Chunhyung Jo;Hagyoul Bae;Hyunjun Choi;Dae Hwan Kim;Dong Myong Kim;]]></authors>
		</item>
		<item>
			<title><![CDATA[Meyer&#x2013;Neldel Rule for Effective Channel Mobility in the Subthreshold Region of Poly-Si Thin-Film Transistors]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6490008]]></link>
			<description><![CDATA[It is verified that the entire subthreshold region of poly-Si thin film transistors (TFTs) is a pseudo-subthreshold region dominated by drift current, where the carrier effective channel mobility is found to follow the Meyer-Neldel rule (MNR). Characteristic MN energies extracted from both metal-induced laterally crystallized poly-Si TFTs and excimer laser annealed TFTs are all close to the optical phonon energy of Si, providing strong evidence to the MNR. Carrier thermionic emission over grain boundary barriers activated by multiphonon absorption process is the origin of the MNR.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6490008]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>644</startPage>
			<endPage>646</endPage>
			<fileSize>530</fileSize>
			<authors><![CDATA[Xiaoliang Zhou;Mingxiang Wang;]]></authors>
		</item>
		<item>
			<title><![CDATA[Bias-Stress-Induced Instabilities in P-Type <formula formulatype="inline"> <img src="/images/tex/19647.gif" alt="{\rm Cu}_{2}{\rm O}"> </formula> Thin-Film Transistors]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502195]]></link>
			<description><![CDATA[We investigate the gate bias-stress-induced instabilities of p-type copper oxide (Cu<sub>2</sub>O) thin-film transistors (TFTs). Transfer curves measured before and after the application of constant gate bias stress under air and vacuum environments show that the partial pressure of the oxygen in the environment does not much affect the transfer characteristics and bias-stress-induced instabilities of the Cu<sub>2</sub>O TFTs. During the negative gate bias stresses, the transfer curves shift to the negative direction without a significant variation of the shape, which is attributed to the hole trapping in the interface or bulk dielectric layers with a negligible creation of additional interface trap states. During the positive gate bias stresses, a threshold voltage hardly moves to the positive direction because of the lack of free electron inside the p-type Cu<sub>2</sub>O, but a notable degradation of the subthreshold slope is observed. From the recovery characteristics, the generated traps during the positive gate bias stress are estimated to be metastable ones in p-type Cu<sub>2</sub>O TFTs.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502195]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>647</startPage>
			<endPage>649</endPage>
			<fileSize>521</fileSize>
			<authors><![CDATA[Ick-Joon Park;Chan-Yong Jeong;Myeonghun, U.;Sang-Hun Song;In-Tak Cho;Jong-Ho Lee;Eou-Sik Cho;Hyuck-In Kwon;]]></authors>
		</item>
		<item>
			<title><![CDATA[Realization of Low Driving Voltage in Organic Light-Emitting Diodes Using <formula formulatype="inline"> <img src="/images/tex/20886.gif" alt="{\rm C}_{60}"> </formula> as an Electron Transport Layer and <formula formulatype="inline"> <img src="/images/tex/20887.gif" alt="{\rm Alq}_{3}"> </formula> as a Buffer Layer]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6496151]]></link>
			<description><![CDATA[Organic light-emitting diodes with low driving voltage based on fullerene (C<sub>60</sub>) as an electron transport layer and tris (8-hydroxyquinolinato)-aluminum (Alq<sub>3</sub>) as a buffer layer are successfully fabricated. For the optimal device with structures of ITO/NPB (40 nm)/Alq<sub>3</sub> /(30 nm)/C<sub>60</sub> (20 nm)/Alq<sub>3</sub> (3 nm)/LiF (0.8 nm)/Al (120 nm), the turn-on driving voltage is 2.8 V, which is reduced 0.4 V compared with that of the control device. Meanwhile, the driving voltage of 4.9 V has been achieved at a luminance of 1000 cd/m<sup>2</sup> in this device, which is reduced 1.8 V compared with that of the control device. The results have a significant effect on the commercialization application of the devices.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6496151]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>650</startPage>
			<endPage>652</endPage>
			<fileSize>472</fileSize>
			<authors><![CDATA[Xiao Ming Wu;Xue Mu;Yu Lin Hua;Juan Juan Bai;Li Wang;Zhi Hui Xiao;Ni Dong;Shou Gen Yin;]]></authors>
		</item>
		<item>
			<title><![CDATA[Novel Silicon Photomultiplier With Vertical Bulk-Si Quenching Resistors]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6484881]]></link>
			<description><![CDATA[A novel structure of silicon photomultiplier (SiPM) is reported. In this structure, a vertical bulk-Si quenching resistor is introduced to replace the poly-Si resistor in the SiPM cell, which can help to improve the fill factor of the SiPM for more efficient photon detection. A current-blocking layer is inserted into the resistor layer to reduce the cross-section of the resistor so that the necessary high quenching resistance can be achieved by the thin resistor layer. The performance of the SiPM cell is confirmed by simulation. The vertical bulk-Si resistors are fabricated and characterized. According to the I-V measurements, the structures achieved show good resistor properties. An equivalent quenching resistance in the order of 10<sup>5</sup> &#x03A9; is observed in a 1-&#x03BC;m-thick resistor.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6484881]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>653</startPage>
			<endPage>655</endPage>
			<fileSize>541</fileSize>
			<authors><![CDATA[Fei Sun;Ning Duan;Guo-Qiang Lo;]]></authors>
		</item>
		<item>
			<title><![CDATA[Enhanced Charge Transfer of QDs/Polymer Hybrid LED by Interface Controlling]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6491439]]></link>
			<description><![CDATA[We propose a quantum dots (QDs)/poly(N-vinylcarbazole) (PVK) hybrid light-emitting diode (LED) to improve the electron and hole confinement in the QDs layer. QDs used as monochromatic emitters are dispersed in a PVK matrix with a wide bandgap for quantum wells. The HOMO and LUMO level of the PVK can act as a hole transport buffer and an electron-blocking buffer in the hybridized layer. We fabricate an LED using a simplified QDs/PVK hybrid emissive layer (EML) and compare its performance with that of the hybrid LED with controlled QDs concentration. From the result, it is found that the 1.0 wt% QDs within the PVK hybrid LED show the best performance among the compared LEDs, with a luminance of 5989 cd/m<sup>2</sup> and an efficiency of 4.2 cd/A. The efficient energy transfer and performance of the QDs/PVK hybrid EML are highly depended on the doping concentration of the QDs.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6491439]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>656</startPage>
			<endPage>658</endPage>
			<fileSize>438</fileSize>
			<authors><![CDATA[Byoung-Ho Kang;Sang-Won Lee;Sung-Woo Lim;Tae-Yang You;Se-Hyuk Yeom;Kyu-Jin Kim;Dae-Hyuk Kwon;Shin-Won Kang;]]></authors>
		</item>
		<item>
			<title><![CDATA[A Surface-Plasmon-Enhanced Silicon Solar Cell With KOH-Etched Pyramid Structure]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502194]]></link>
			<description><![CDATA[A pyramid structure etched with KOH solution was employed on a silicon (Si) surface to increase the absorbing path length of light; subsequently, gold (Au) nanoparticles (NPs) were deposited on the etched surface. Solar cells with and without KOH etching or Au NPs are fabricated to study the effects of KOH etching and Au NPs on the characteristics of solar cells. Due to the larger surface area etched by KOH, more Au NPs adhere to the Si surface, and hence more surface plasmon oscillations are induced by the incident light. For the incident wavelength longer than the oscillation wavelength of Au NPs (550 nm), constructive interference occurs, which enhances the short-circuit current density and conversion efficiency. In contrast, for a wavelength smaller than 550 nm, absorption dominates the extinction spectra. The short-circuit current density and conversion efficiency of the solar cells with KOH etching and Au NPs increase by 26.8% and 28.5%, respectively, compared with that of the solar cells without KOH etching and without Au NPs.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502194]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>659</startPage>
			<endPage>661</endPage>
			<fileSize>364</fileSize>
			<authors><![CDATA[Jun-Dar Hwang;Don-Ru Hsieh;]]></authors>
		</item>
		<item>
			<title><![CDATA[Solution-Based PbS Photodiodes, Integrable on ROIC, for SWIR Detector Applications]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502656]]></link>
			<description><![CDATA[Photodiodes, based on PbS colloidal quantum dots (CQD), are realized on both silicon substrates and the replicas of the read-out integrated circuits (ROICs) to demonstrate the first, fully integrated focal plane arrays. Careful optimization of PbS CQD film formation and ligand exchange process, together with optimized process steps, resulted in high performance, monolithically integrable photodiodes. High quantum efficiencies of 32% are achieved for photodiodes on Si substrates and high responsivities up to 5.73 A/W is achieved for photodiodes on ROIC replicas. These detectors achieved very high, normalized detectivities of 1.36 &#x00D7; 10<sup>11</sup> Jones and 1.42 &#x00D7; 10<sup>12</sup> Jones under 1 and 2-V reverse bias, respectively, that are close to conventional InGaAs short wave infrared detectors.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502656]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>662</startPage>
			<endPage>664</endPage>
			<fileSize>423</fileSize>
			<authors><![CDATA[Heves, E.;Ozturk, C.;Ozguz, V.;Gurbuz, Y.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Enhancement of Open-Circuit Voltage Using <formula formulatype="inline"> <img src="/images/tex/19014.gif" alt="{\rm CF}_{4}"> </formula> Plasma Treatment on Nitric Acid Oxides]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6495702]]></link>
			<description><![CDATA[Surface passivation of solar cells is investigated using CF<sub>4</sub> plasma treatment on low-temperature oxides to enhance the open-circuit voltage of the solar cells. Low-temperature oxides grown by a nitric acid solution are treated with the CF<sub>4</sub> plasma. Solar cells undergoing this scheme show an improved performance, including low-saturation current density and good quantum efficiency at short wavelengths. Experimental results demonstrate that the CF<sub>4</sub> plasma pretreatment on low-temperature oxides can significantly improve the open-circuit voltage, short-circuit current, and fill factor for silicon wafer-based solar cells. This technique is very promising for in-line solar cell manufacturing.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6495702]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>665</startPage>
			<endPage>667</endPage>
			<fileSize>396</fileSize>
			<authors><![CDATA[Je-Wei Lin;Chien-Hung Wu;Sheng-Wei Wu;Wei-Ping Hseih;Chen-Hsu Du;Tien-Sheng Chao;]]></authors>
		</item>
		<item>
			<title><![CDATA[Electrical and Thermal Properties of Carbon-Nanotube Composite for Flexible Electric Heating-Unit Applications]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6480910]]></link>
			<description><![CDATA[Highly conducting carbon nanotubes (CNTs)/polydimethylsiloxane (PDMS) composite with a low concentration (5.7 vol.%) has been shown to be applicable in a highly controllable electric heating element. Due to a high shear-processing technique for mixing CNTs into an uncured PDMS matrix, the CNT/PDMS composites have a fairly uniform dispersion and no agglomeration of CNTs. The percolation threshold of the prepared CNT/PDMS composite is achieved ~ 0.03 vol.%, which is one of the lowest values previously reported in the literature. The fabricated CNT/PDMS composites can be quickly heated from room temperature to 200&#x00B0;C within 30 s by applying a DC voltage of 12 V. In addition, the CNT/PDMS composite show good thermal stability and repeatability during a long-term heating test. Our proposed CNT/PDMS composites could be used as a basis for light-weight and flexible heating-unit applications.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6480910]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>668</startPage>
			<endPage>670</endPage>
			<fileSize>582</fileSize>
			<authors><![CDATA[Kunmo Chu;Dongouk Kim;Yoonchul Sohn;Sangeui Lee;Changyoul Moon;Sunghoon Park;]]></authors>
		</item>
		<item>
			<title><![CDATA[Sealing Bump With Bottom-Up Cu TSV Plating Fabrication in 3-D Integration Scheme]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6482589]]></link>
			<description><![CDATA[A sealing bump approach for the simplification of the conventional bottom-up copper through-silicon via (TSV) plating process flow is developed to reduce the process steps and increase the throughput without sacrificing the structure integrity and electrical performance. In this approach, TSV and bump formation can be achieved simultaneously through the bottom-up plating. Results from the analysis reveal excellent electrical characteristics and quality examination, which indicate that the proposed approach may be a good candidate for the TSV fabrication in 3-D integration.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6482589]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>671</startPage>
			<endPage>673</endPage>
			<fileSize>648</fileSize>
			<authors><![CDATA[Cheng-Hao Chiang;Li-Min Kuo;Yu-Chen Hu;Wen-Chun Huang;Cheng-Ta Ko;Kuan-Neng Chen;]]></authors>
		</item>
		<item>
			<title><![CDATA[A Latchup-Immune and Robust SCR Device for ESD Protection in 0.25-<formula formulatype="inline"> <img src="/images/tex/16813.gif" alt="\mu{\rm m}"> </formula> 5-V CMOS Process]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6491440]]></link>
			<description><![CDATA[Based on good electrostatic discharge (ESD) robustness, silicon-controlled rectifier (SCR) device is used for on-chip ESD protection. The major concern of SCR is the latch-up issue, because of its low holding voltage. Previous papers tried to design latchup-immune SCR devices; however, those devices would cause lower ESD robustness. In this letter, a new latchup-immune and robust SCR device for ESD protection is proposed and verified in a 0.25-<formula formulatype="inline"><tex Notation="TeX">$mu{rm m}$</tex></formula> 5-V CMOS process. Through inserting one additional parasitic bipolar junction transistor into SCR device structure, this new proposed SCR can increase the holding voltage without causing degradation on its ESD robustness.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6491440]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>674</startPage>
			<endPage>676</endPage>
			<fileSize>329</fileSize>
			<authors><![CDATA[Huang, Y.-C.;Ker, M.-D.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Origin of Hopping Conduction in Graphene-Oxide-Doped Silicon Oxide Resistance Random Access Memory Devices]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6488720]]></link>
			<description><![CDATA[In this letter, a double-active-layer (Zr:SiO<i>x</i>/C:SiO<i>x</i>) resistive switching memory device with a high on/off resistance ratio and small working current (0.02 mA), is presented. Through the analysis of Raman and Fourier transform infrared spectroscopy spectra, we find that graphene oxide exists in the C:SiO<i>x</i> layer. It can be observed that Zr:SiO<i>x</i>/C:SiO<i>x</i> structure has superior switching performance and higher stability compared with the single-active-layer (Zr:SiO<i>x</i>) structure, which is attributed to the existence of graphene oxide flakes formed during the sputter process. <i>I</i>-<i>V</i> characteristics under a series of increasing temperature were analyzed to testify the carrier hopping distance variation, which is further verified by our graphene oxide redox reaction model.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6488720]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>677</startPage>
			<endPage>679</endPage>
			<fileSize>457</fileSize>
			<authors><![CDATA[Kuan-Chang Chang;Rui Zhang;Ting-Chang Chang;Tsung-Ming Tsai;Lou, J.C.;Jung-Hui Chen;Tai-Fa Young;Min-Chen Chen;Ya-Liang Yang;Yin-Chih Pan;Geng-Wei Chang;Tian-Jian Chu;Chih-Cheng Shih;Jian-Yu Chen;Chih-Hung Pan;Yu-Ting Su;Yong-En Syu;Ya-Hsiang Tai;Sze, S.M.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Charge Transport and Degradation in <formula formulatype="inline"> <img src="/images/tex/681.gif" alt="{\rm HfO}_{2}"> </formula> and <formula formulatype="inline"> <img src="/images/tex/20884.gif" alt="{\rm HfO}_{\rm x}"> </formula> Dielectrics]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6487378]]></link>
			<description><![CDATA[We combine experiments and simulations to investigate leakage current and breakdown (BD) in stoichiometric and sub-stoichiometric hafnium oxides. Using charge-transport simulations based on phonon-assisted carrier tunneling between trap sites, we demonstrate that higher currents generally observed in HfO<sub>x</sub> are due to a higher density of the as-grown oxygen vacancy defects assisting the charge transport. Reduction of the dielectric BD field (<i>E</i><sub>BD</sub>) in HfO<sub>x</sub> is explained by the lower zero-field activation energy (<i>E</i><sub>A,G</sub>) of the defect generation process, as extracted from time-dependent dielectric BD experiments.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6487378]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>680</startPage>
			<endPage>682</endPage>
			<fileSize>928</fileSize>
			<authors><![CDATA[Padovani, A.;Larcher, L.;Bersuker, G.;Pavan, P.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Investigation of the RTN Distribution of Nanoscale MOS Devices From Subthreshold to On-State]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6491437]]></link>
			<description><![CDATA[This letter presents a numerical investigation of the statistical distribution of the random telegraph noise (RTN) amplitude in nanoscale MOS devices, focusing on the change of its main features when moving from the subthreshold to the on-state conduction regime. Results show that while the distribution can be well approximated by an exponential behavior in subthreshold, large deviations from this behavior appear when moving toward the on-state regime, despite a low probability exponential tail at high RTN amplitudes being preserved. The average value of the distribution is shown to keep an inverse proportionality to channel area, while the slope of the high-amplitude exponential tail changes its dependence on device width, length, and doping when moving from subthreshold to on-state.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6491437]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>683</startPage>
			<endPage>685</endPage>
			<fileSize>328</fileSize>
			<authors><![CDATA[Amoroso, S.M.;Compagnoni, C.M.;Ghetti, A.;Gerrer, L.;Spinelli, A.S.;Lacaita, A.L.;Asenov, A.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Statistical Interactions of Multiple Oxide Traps Under BTI Stress of Nanoscale MOSFETs]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502190]]></link>
			<description><![CDATA[We report a thorough 3-D simulation study of the correlation between multiple, trapped charges in the gate oxide of nanoscale bulk MOSFETs under bias and temperature instability (BTI). The role of complex electrostatic interactions between the trapped charges in the presence of random dopant fluctuations is evaluated, and their impact on the distribution of the threshold voltage shift and on the distribution of the number of trapped charges is analyzed. The results justify the assumptions of a Poisson distribution of the BTI-induced trapped charges and of the lack of correlation between them, when accounting for time-dependent variability in circuits.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502190]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>686</startPage>
			<endPage>688</endPage>
			<fileSize>763</fileSize>
			<authors><![CDATA[Markov, S.;Amoroso, S.M.;Gerrer, L.;Adamu-Lema, F.;Asenov, A.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Terahertz Continuous Wave Detection Using Weakly Ionized Plasma in Inert Gases]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6495470]]></link>
			<description><![CDATA[A weakly ionized plasma detector was designed for the terahertz (THz) continuous wave detection. The effect of inert gas pressure, components, and discharge current on the detector's responsivity and stability was investigated. Experiment results reveal that the detector's responsivity can be as high as 194.4 V/W and its signal-to-noise ratio can reach 560 at 0.187 THz.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6495470]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>689</startPage>
			<endPage>691</endPage>
			<fileSize>209</fileSize>
			<authors><![CDATA[Lei Hou;Wei Shi;Suguo Chen;Zhijin Yan;]]></authors>
		</item>
		<item>
			<title><![CDATA[Wafer-Level Fabrication of a Fused-Quartz Double-Ended Tuning Fork Resonator Oscillator Using Quartz-on-Quartz Direct Bonding]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502191]]></link>
			<description><![CDATA[In this letter, a novel process to fabricate high-<i>Q</i> fused-quartz micromechanical resonators is demonstrated. Plasma-assisted quartz-on-quartz direct bonding at a low temperature in combination with quartz deep-reactive ion etching technique enables a simple wafer-level fabrication of self-mounted, electrostatically driven fused-quartz resonators. A 27-kHz capacitively transduced double-ended tuning fork fused-quartz resonator oscillator is successfully fabricated using the developed process. A high resonator <i>Q</i>-factor of 68000 is obtained, and the constructed oscillator shows a signal-to-noise ratio of 70 dB.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502191]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>692</startPage>
			<endPage>694</endPage>
			<fileSize>499</fileSize>
			<authors><![CDATA[Eun-Seok Song;Sungmuk Kang;Hoseong Kim;Yong-Kweon Kim;Jun-Eon An;Chang-Wook Baek;]]></authors>
		</item>
		<item>
			<title><![CDATA[Dosimetric Performance of Single-Crystal Diamond X-Ray Schottky Photodiodes]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502655]]></link>
			<description><![CDATA[Single-crystal diamond Schottky photodiodes have been developed following a WC-diamond-TiC/Ti/Ag vertical structure for X-ray dosimetry with characteristics of low leakage current and the capability of zero-bias operations. Continuous and modulated X-ray measurements show that the devices developed provide a linear response to dose rate at low bias voltages (&lt;; 2.5 V) and at modulation frequencies &gt; 130 Hz. This supports their application in modulated radiotherapy treatments.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502655]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>695</startPage>
			<endPage>697</endPage>
			<fileSize>717</fileSize>
			<authors><![CDATA[Bellucci, A.;Orlando, S.;Caputo, D.;Cappelli, E.;Trucchi, D.M.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Carbon Nanotube Cathodes for Electron Gun]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6490007]]></link>
			<description><![CDATA[Two carbon nanotubes cold cathodes, employable in electron guns for linear vacuum tubes (traveling-wave tubes, Klystron), are realized considering an extracting grid in two different configurations: integrated or externally mounted. The electron field emission of the two cathodes is measured to compare the two devices. In an external extracting grid, a transparency of 72% and a maximum current density of 3.2 mA/cm<sup>2</sup> are obtained, whereas in the integrated grid device, a transparency of 75% and a maximum current density of 74 mA/cm<sup>2</sup> are obtained. The high transparency achieved makes the two cathodes attractive for low power consumption vacuum tubes.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6490007]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>698</startPage>
			<endPage>700</endPage>
			<fileSize>815</fileSize>
			<authors><![CDATA[Ulisse, G.;Brunetti, F.;Tamburri, E.;Orlanducci, S.;Cirillo, M.;Terranova, M.L.;Carlo, A.D.;]]></authors>
		</item>
		<item>
			<title><![CDATA[UV Enhanced Field Emission for <formula formulatype="inline"> <img src="/images/tex/20891.gif" alt="\beta \hbox {-}{\rm Ga}_{2}{\rm O}_{3}"> </formula> Nanowires]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502192]]></link>
			<description><![CDATA[This letter presents vapor-liquid-solid growth of &#x03B2;-Ga<sub>2</sub>O<sub>3</sub> nanowires (NWs) on cost-effective SiO<sub>2</sub>/Si template and the fabrication of &#x03B2;-Ga<sub>2</sub>O<sub>3</sub> NW field emitters. It is found that the &#x03B2;-Ga<sub>2</sub>O<sub>3</sub> NWs grown at 950<sup>&#x00B0;</sup>C are structurally uniform, defect free, and well-oriented with pure monoclinic structure. It is also found that turnon fields are 2.0, 3.9, and 5.8 V/&#x03BC;m whereas field-enhancement factors &#x03B2; are 1890, 2760, and 4489, for the samples grown at 850<sup>&#x00B0;</sup>C, 900 <sup>&#x00B0;</sup>C, and 950<sup>&#x00B0;</sup>C, respectively. For the sample prepared at 950<sup>&#x00B0;</sup>C, it is found that we could further reduce the turnon field from 2 to 1.2 V/&#x03BC;m whereas enhance the field-enhancement factor &#x03B2; from 4489 to 6926 by ultraviolet irradiation.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502192]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>701</startPage>
			<endPage>703</endPage>
			<fileSize>741</fileSize>
			<authors><![CDATA[Wu, Y.L.;Shoou-Jinn Chang;Liu, C.H.;Wen-Yin Weng;Tsung-Ying Tsai;Cheng-Liang Hsu;]]></authors>
		</item>
		<item>
			<title><![CDATA[Field Emitter Equipped With a Suppressor to Control Emission Angle]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6495703]]></link>
			<description><![CDATA[We introduce a suppressor electrode into a micro-sized field emitter to control the emission angle, as an alternative to using an aperture. The suppressor electrode is fabricated between the emission tip and the extractor by using an etch-back technique. The suppressor height is determined to be 100 nm below the tip. This structure is expected to control the emission angle to be narrower when applying a low voltage at the suppressor electrode. The emission characteristics of the fabricated device closely follow the behavior of the simulated results. It is shown that the emission angle is narrowed by applying a negative voltage at the suppressor electrode.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6495703]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>704</startPage>
			<endPage>706</endPage>
			<fileSize>1114</fileSize>
			<authors><![CDATA[Koike, A.;Neo, Y.;Mimura, H.;Murata, H.;Yoshida, T.;Nishi, T.;Nagao, M.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Hydrogenation of Graphene Nanoribbon Edges: Improvement in Carrier Transport]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502199]]></link>
			<description><![CDATA[This letter is the first to present a method to selectively hydrogenate the edges of sub-30-nm graphene nanoribbons (GNRs). After hydrogenation of the edges, the GNRs exhibit improved transport properties; carrier mobility increases by up to 50% at a carrier density of <formula formulatype="inline"><tex Notation="TeX">$5times 10^{12}~{rm cm}^{-2}$</tex></formula> at room temperature.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6502199]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>707</startPage>
			<endPage>709</endPage>
			<fileSize>900</fileSize>
			<authors><![CDATA[Zheng, P.;Bryan, S.E.;Yang, Y.;Murali, R.;Naeemi, A.;Meindl, J.D.;]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Electron Devices Society Meetings Calendar (As of 3/29/2013)]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6506862]]></link>
			<description><![CDATA[Provides a notice of upcoming conference events of interest to practitioners and researchers.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6506862]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>710</startPage>
			<endPage>711</endPage>
			<fileSize>1138</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Electron Device Letters information for authors]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6506856]]></link>
			<description><![CDATA[Provides instructions and guidelines to prospective authors who wish to submit manuscripts.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6506856]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>712</startPage>
			<endPage>712</endPage>
			<fileSize>111</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[Special issue on advanced FET compact models for future technology generations]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6506854]]></link>
			<description><![CDATA[Provides a notice of upcoming special issue(s) of interest to practitioners and researchers.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6506854]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>713</startPage>
			<endPage>713</endPage>
			<fileSize>308</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[Special issue on vacuum electronic devices]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6506861]]></link>
			<description><![CDATA[Provides a notice of upcoming special issue(s) of interest to practitioners and researchers.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6506861]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>714</startPage>
			<endPage>714</endPage>
			<fileSize>233</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[Table of contents]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6506852]]></link>
			<description><![CDATA[Presents the cover/table of contents for this issue of the periodical.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6506852]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>715</startPage>
			<endPage>C3</endPage>
			<fileSize>166</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[[Blank page - back cover]]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6506857]]></link>
			<description><![CDATA[This page or pages intentionally left blank.]]></description>
			<pubDate><![CDATA[May  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6506857]]></guid>
			<volume>34</volume>
			<issue>5</issue>
			<startPage>C4</startPage>
			<endPage>C4</endPage>
			<fileSize>5</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
	</channel>
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