<![CDATA[ IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - new TOC ]]>
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TOC Alert for Publication# 43 2016June 23<![CDATA[Table of contents]]>357C1C1415<![CDATA[IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information]]>357C2C2156<![CDATA[PolyPUF: Physically Secure Self-Divergence]]>357105310661340<![CDATA[P-Val: Antifuse-Based Package-Level Defense Against Counterfeit ICs]]>357106710781659<![CDATA[An Integrated Approach for Managing Read Disturbs in High-Density NAND Flash Memory]]>357107910912583<![CDATA[Mapping Imperfect Loops to Coarse-Grained Reconfigurable Architectures]]>357109211041763<![CDATA[Full-Component Modeling and Simulation of Charged Device Model ESD]]>357110511131976<![CDATA[Fast Thermal Simulation of FinFET Circuits Based on a Multiblock Reduced-Order Model]]>357111411241648<![CDATA[Improving Computing Systems Automatic Multiobjective Optimization Through Meta-Optimization]]>35711251129440<![CDATA[A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse]]>${J} ^{{-1}}$ ) is reused to simulate many circuits whose solutions are similar. GALAXY also speeds up single-circuit simulation by reusing ${J} ^{{-1}}$ between consecutive time steps. Compared with a traditional Newton–Raphson (NR) simulator, on average, GALAXY reduces runtime of single-circuit and multicircuit simulation by 44% and 71%, without loss of accuracy. The number of NR iterations is reduced by 78%.]]>357113011371516<![CDATA[Compact Model Parameter Extraction Using Bayesian Inference, Incomplete New Measurements, and Optimal Bias Selection]]>a posteriori estimation where past measurements of transistors from various technologies are used to learn a prior distribution and its uncertainty matrix for the parameters of the target technology. The framework then utilizes Bayesian inference to facilitate extraction using a very small set of additional measurements. The proposed method is validated using various past technologies and post-silicon measurements for a commercial 28-nm process. The proposed extraction can be used to characterize the statistical variations of MOSFETs with the significant benefit that the restrictions imposed by the backward propagation of variance algorithm are relaxed. We also study the lower bound requirement for the number of transistor measurements needed to extract a full set of parameters for a compact model. Finally, we propose an efficient algorithm for selecting the optimal transistor biases by minimizing a cost function derived from information-theoretic concept of average marginal information gain.]]>357113811502193<![CDATA[Toward a Profitable Grid-Connected Hybrid Electrical Energy Storage System for Residential Use]]>357115111641764<![CDATA[An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization]]>$2.2 {times }$ on average on NVIDIA GTX480.]]>357116511782163<![CDATA[Fault Diagnosis for Leakage and Blockage Defects in Flow-Based Microfluidic Biochips]]>357117911911992<![CDATA[A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs]]>357119212053273<![CDATA[Efficient Symbolic Computation for Word-Level Abstraction From Combinational Circuits for Verification Over Finite Fields]]>${Z} {= {mathcal {F}}(A)}$ over the finite field $ {{mathbb {F}}_{2^{k}}}$ , where ${Z}$ and $ {A}$ represent the ${k}$ -bit output and input bit-vectors (words) of the circuit, respectively. This canonical abstraction can be utilized for formal verification and equivalence checking of combinational circuits. Our approach to abstraction is based upon concepts from computational commutative algebra and algebraic geometry. We show that the abstraction ${Z} {= {mathcal {F}}(A)}$ can be derived by computing a Gröbner basis of the polynomials corresponding to the circuit, using a specific elimination term order derived from the circuit’s topology. Computing Gröbner bases using elimination term orders is infeasible for large circuits. To overcome this limitation, we describe an efficient symbolic computation to derive the word-level polynomial. Our algorithms exploit: 1) the structure of the circuit; 2) the properties of Gröbner bases; 3) characteristics of finite fields $ {{mathbb {F}}_{2^{k}}}$ ; and 4) modern algorithms from symbolic algebra, to derive the canonical polynomial representation. This approach is employed to verify (and detect bugs in) large combinational finite field arithmetic circuits, where contemporary verific-
tion techniques are known to be infeasible.]]>35712061218849<![CDATA[Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores]]>35712191223989<![CDATA[A SVM Surrogate Model-Based Method for Parametric Yield Optimization]]>35712241228695<![CDATA[IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information]]>357C3C3246<![CDATA[IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors]]>357C4C4195