<![CDATA[ IET Circuits, Devices & Systems - new TOC ]]>
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TOC Alert for Publication# 4123966 2017February 23<![CDATA[Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection]]>11119592<![CDATA[On the realisation of canonic single-resistance-controlled oscillators using third generation current conveyors]]>11110201234<![CDATA[Adaptive line voltage compensation scheme for a source-driving controlled AC–DC LED driver]]>T_{Demag} and switching period T_{S} and the primary peak current are remained constant by the proposed control IC, obtaining constant current output. Meanwhile, an adaptive line voltage compensation circuit, integrated in the primary peak current controller, is proposed based on source-driving control scheme. A compensation current proportional to line voltage is injected to the primary-side current sampling pin CS, thus making the turn-off bandgap reference of primary peak current under high-line voltage lower than that under low-line voltage. As a consequence, overshoot phenomena of primary peak current can be avoided, and the line regulation as well as the precision of output current can be improved. The proposed control IC has been fabricated in TSMC 0.35 μm 5 V/650 V CMOS/LDMOS process. Experimental results of a 5 W prototype show that the output current is kept stable at ~250 mA, and the line regulation is within ±0.5% in a wide range of universal-input ac voltage from 85 to 264 V, and that >80% efficiency is obtained under heavy LED loads.]]>1112128910<![CDATA[Design of multiplierless prototype filter for two-channel filter bank using hybrid method in FCSD space]]>A_{s}) and roll-off factor. Windowing method has been used for efficient design of a prototype filter with novelty of exploiting quantised coefficients in canonical sign digit (CSD) and factorised canonical sign digit (FCSD) space by merging the concept of particle swarm optimisation and artificial bee colony algorithm. The quantised filter coefficients are optimised by varying cut-off frequency such that the magnitude response of prototype filter is approximately reduced to 0.707 at quadrature frequency. The implemented filter is synthesised using target field programmable gate arrays XC3S500E-4-FG320 on Xilinx Spartan 3E starter board. The performances of designed prototype filter is compared with the earlier published works in terms of reconstruction error, amplitude distortion, slices, flip-flops, four-input lookup tables and adders. The synthesis results demonstrate that the significant reduction in hardware is achieved in term of adder gain. For filter order, N = 32, and word length 12, the adder gain achieved in CSD and FCSD is 41.77 and 43.07%, respectively, while for N = 30, it is 35.44% in CSD and 36.70% in FCSD, respectively.]]>1112940812<![CDATA[Systematic synthesis approach for floating gyrators employing single <italic>z</italic>-copy CCCCTA]]>z-copy current-controlled current conveyor trans-conductance amplifier (CCCCTA) is presented in this work. Initially, the pathological models of two types of the CCCCTA, namely z-copy z_{+}-output CCCCTA (CCCCTA+) and z-copy z_{-}-output CCCCTA (z-copy CCCCTA-), are derived by virtue of the nodal admittance matrix (NAM) expansion method. Moreover, these models are then used in the synthesis of floating gyrator using single z-copy CCCCTA. Two floating gyrators are acquired by expanding the NAM of floating gyrator. The synthesised gyrators employ one z-copy CCCCTA and a grounded admittance. Adjusting bias currents of the CCCCTA can tune the parameter of the gyrators. The hand analysis and PSPICE simulation show that the used synthesis method is simple, systematic and valid.]]>1114145546<![CDATA[A new approach for designing compressors with a new hardware-friendly mathematical method for multi-input XOR gates]]>11146571282<![CDATA[Reversible logic-based image steganography using quantum dot cellular automata for secure nanocommunication]]>11158671535<![CDATA[Dynamics and control of voltage multiplier cells integrated boost converter]]>11168791499<![CDATA[Spacer engineering for performance enhancement of junctionless accumulation-mode bulk FinFETs]]>g_{m}), transconductance generation factor (g_{m}/I_{d}), cut-off frequency (f_{T}), maximum frequency of oscillation (f_{max}) and so on. The device under study shows better ON-OFF current ratio, transconductance, transconductance generation factor using gate spacer having high k-value. However, because of increased gate capacitances, its RF performance degrades with increase in dielectric constant of the spacer used. The effects of downscaling of channel length (L) on analogue performance of the proposed junctionless accumulation mode device have also been presented. It has been observed that the analogue/RF performance of the device can be improved by reducing the spacer length.]]>11180881196<![CDATA[AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement]]>1118994450<![CDATA[Contactless power transmission for NFC antennas in credit-card size format]]>11195101308