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TOC Alert for Publication# 4123966 2018February 19<![CDATA[Design of high-speed, low-power, and area-efficient FIR filters]]>r. The latter exhibits the best results in speed and power, comparatively with the most prominent algorithms. In this paper, the area aspect of RADIX-2^{r} is more specially investigated. RADIX-2^{r} is confronted to area efficient algorithms, notably to the cumulative benefit heuristic (Hcub) known for its lowest adder-cost. A number of benchmark FIR filters of growing complexity served for comparison. The results showed that RADIX-2^{r} is better than Hcub in area, especially for high order filters where the saving ranges from 1.50% up to 3.46%. This advantage is analytically proved and experimentally confirmed using a 65nm CMOS technology. Area efficiency is achieved along with important savings in speed and power, ranging from 6.37% up to 38.01% and from 9.30% up to 25.85%, respectively. When MCM blocks are implemented alone, the savings are higher: 10.18%, 47.24%, and 41.27% in area, speed, and power, respectively. Most importantly, we prove that MCM heuristics using similar addition pattern (A-operation with the same shift spans) as Hcub yield excessive bit-adder overhead in MCM problems of high complexity. As such, they are not competitive to RADIX-2^{r} in high order filters.]]>1211111837<![CDATA[3–10 GHz noise-cancelling CMOS LNA using g<italic><sub>m</sub></italic>-boosting technique]]>g_{m}-boosting technique using the noise-cancelling CS stage without additional amplifier, and the noise performance can be improved at the same power consumption. For low-power operation, the LNA consumes 2.9 mW and achieves a noise figure (NF) of S_{21} between 16.5 and 17.6 dB at S_{11}, lower than -12.4 and 3.6-3.7 dB at frequencies of 3-10 GHz. In low-noise operation, the LNA consumes 8.3 mW, achieving S_{11} of less than -10.7 dB, S_{21} of 17.5-18.7 dB, and NF of 2.4-2.9 dB.]]>12112161602<![CDATA[Low-jitter DLL applied for two-segment TDC<?show [AQ ID=Q1]?>]]>12117244873<![CDATA[Reduced <inline-formula><alternatives><tex-math notation="TeX">$H_2$</tex-math><mml:math overflow="scroll"><mml:msub><mml:mi>H</mml:mi><mml:mn>2</mml:mn></mml:msub></mml:math><inline-graphic xlink:href="IET-CDS.2016.0430.IM1.gif" /></alternatives></inline-formula> optimal models via cross Gramian for continuous linear time-invariant systems]]>2 optimal MOR iterative algorithm to reduce the SISO system. Further, the authors explore the H_{2} optimisation problem on the Stiefel manifold. Based on the geometric notions on this manifold, a conjugate gradient iterative algorithm (CGIAHM) is proposed. The conjugate gradient direction used to search for the H_{2} minimiser is derived by applying the notion of vector transport. It is worth mentioning that the conjugate gradient used in the CGIAHM algorithm is a decent direction for the cost function due to the ingenious construction of this algorithm. In addition, the authors' algorithms are extended to solve the H_{2} optimal MOR problem for general LTI systems. Finally, two numerical examples demonstrate the effectiveness of their algorithms.]]>12125322126<![CDATA[Hybrid AlGaN/GaN high-electron mobility transistor: design and simulation]]>g_{m}) by 168%, cutoff frequency (f_{T}) by 71% and maximum oscillation frequency (f_{max}) by 65% in comparison to the conventional HEMT.]]>12133393642<![CDATA[Design of rectenna series-association circuits for radio frequency energy harvesting in CMOS FD-SOI 28 nm]]>12140498248<![CDATA[Improvement of two-step write scheme in complementary resistive switch array]]>12150542016<![CDATA[Self-compensation scheme for truncation error in fixed width multipliers]]>12155624568<![CDATA[Direct interfacing circuit-based e-nose for gas classification and its uncertainty estimation]]>12163722324<![CDATA[Low-voltage fully differential difference transconductance amplifier]]>12173814087<![CDATA[RC oscillators based on high-<italic>Q</italic> frequency-selecting network]]>Q band-pass filter and a voltage amplifier is transformed into a current-mode oscillator employing a trans-conductance amplifier. Furthermore, a current-mode quadrature oscillator with a high-Q band-pass filter and second generation current-controlled conveyors (CCCIIs) is presented. Since the loop of the oscillator has rich selectivity, the oscillator produces less distortion. Also, the 3 dB bandwidth, oscillation criterion, and oscillation frequency of the oscillator could independently, linearly, and electronically be tuned by the aid of adjusting bias currents of the CCCIIs. Finally, the validity of the designed circuit is verified by means of the computer simulation and the non-ideal analysis is performed to explain the results of the simulation. The results show that the designed circuit is workable.]]>12182871995<![CDATA[Dual frequency MEMS resonator through mixed electrical and mechanical coupling scheme]]>12188933053<![CDATA[Charge sharing write driver and half-<inline-formula><alternatives><tex-math notation="TeX">$V_{{rm DD}}$</tex-math><mml:math overflow="scroll"><mml:msub><mml:mi>V</mml:mi><mml:mrow><mml:mrow><mml:mi mathvariant="normal">DD</mml:mi></mml:mrow></mml:mrow></mml:msub></mml:math><inline-graphic xlink:href="IET-CDS.2017.0146.IM1.gif" /></alternatives></inline-formula> pre-charge 8T SRAM with virtual ground for low-power write and read operation]]>DD read BL (RBL) pre-charge scheme is presented for a single-ended 8T static random access memory (SRAM). Before write enable (WE) signal assertion, CSWD equalises the write BLs by allowing their charge sharing. Both write BLs are equalised at the middle value of supply voltage using leakage current compensation block. Afterwards, as WE signal is asserted, CSWD produces the rail-to-rail levels at write BL pair. Charging of a BL from half-V_{DD} to V_{DD} essentially reduces the write dynamic power dissipation by 50%. Half-V_{DD} precharging is used for RBL to achieve low-power read operation. Read port is powered by virtual ground rail to improve the RBL leakages. The authors compare the proposed 8T design (P8T) with conventional 6T (C6T) and 8T (C8T) designs in a 45 nm technology node. Write power dissipation is reduced by 42% and dynamic read power is reduced by more than 39%. Overall leakages are reduced by more than 18% compared with C6T and I_{on}/I_{off} ratio of the RBL is improved by more than two orders of magnitude compared with conventional 8T (C8T).]]>12194983034<![CDATA[Low-jitter spread spectrum clock generator using charge pump frequency detector in 0.18 μm CMOS for USB3.1 transceivers<?show [AQ ID=Q1]?>]]>2 active area. Based on simulation results, with a 1.8 V supply, it consumes 53.46 mW. The RMS value of absolute jitter at 5 GHz output of non-spread spectrum is 1.1 ps rms, and the EMI reduction is 22.7 dB with -5000 ppm down spread. The simulation results of the proposed system are compared with recent works.]]>121991076135<![CDATA[Hardware design of multiclass SVM classification for epilepsy and epileptic seizure detection]]>1211081151854<![CDATA[Accurate performance evaluation of VLSI designs with selected CMOS process parameters]]>1211161234889<![CDATA[Six-bit, reusable comparator stage-based asynchronous binary-search SAR ADC using smart switching network]]>N comparators in comparison with original binary-search ADC and flash ADC. The design uses selection logic which selects and activates the comparator one at a time, and a smart switching network which allocates reference voltage to selected comparators in the successive comparison process. It claims for equipoise with power and operating speed when compared with flash ADC and SAR ADC. The post-layout simulated performance of 6 bit conversion using only six comparators on United Microelectronics Corporation (UMC)-180 nm achieves 41 dB spurious-free dynamic range and 36.02 dB signal-to-noise distortion ratio with a maximum sampling speed of 330 MS/s consuming 0.64 mW power when operated at 1.8 V supply, corresponding figure-of-merit 36.47 fJ/conversion step.]]>1211241315441