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TOC Alert for Publication# 4117424 2014July 07<![CDATA[Methodology for adapting on-chip interconnect architectures]]>83109117696<![CDATA[Column selection solutions for L1 data caches implemented using eight-transistor cells]]>831181281304<![CDATA[Approach to design a compact reversible low power binary comparator]]>n-bit binary comparator. An algorithm is presented for constructing a compact reversible n-bit binary comparator circuit. The authors also propose two new reversible gates, namely, Babu-Jamal-Saleheen (BJS) and Hasan-Lafifa-Nazir (HLN) gates, to optimise the comparator. In addition, several theorems on the numbers of gates, garbage outputs, quantum cost, ancilla input, power, delay and area of the reversible n-bit comparator have been presented. The simulation results of the proposed comparator show that the circuit works correctly and gives significantly better performance than the existing ones. The comparative study shows that, as an example, for a 64-bit comparator, the proposed design achieves the improvement of 24.4% in terms of number of gates, 19.9% in terms of garbage outputs, 7.7% in terms of quantum cost, 25.77% in terms of area and 3.43% in terms of power over the existing best one. Area and power analysis also show that the proposed design is the most compact as well as a low power circuit.]]>83129139590<![CDATA[Single event transient tolerant frequency divider]]>83140147503<![CDATA[eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip]]>831481622769