http://ieeexplore.ieee.org TOC Alert for Publication# 4 2012 February 10 47 2 C1 C4 125 47 2 C2 C2 39 47 2 357 358 123 $mu$m BiCMOS process. The power consumption is reduced by using a single-ended design and alternating the amplifiers and phase shifter cells to result in a low noise figure at a low power consumption. A variable gain amplifier and an 11$^{circ}$ trim bit are used to correct for the rms gain and phase errors at different operating frequencies. The phased array consumes 32 mW per channel and results in a gain of 10–19 dB at 76–84 GHz, a noise figure of 10.5 ${pm}$0.5 dB at 80 GHz and an rms gain and phase error ${<}$0.8 dB and ${< }$7.2 $^{circ}$, respectively, up to 81 GHz, and ${<}$1.1 dB and 10.4$^{circ}$ up to 84 GHz. The phased array also shows a channel to channel coupling of ${<}{-}$ 30 dB up to 84 GHz. To our knowledge, this work presents state-of-the-art on-chip performance at W-band frequencies.]]> 47 2 359 367 2485 $Q$-band (40–45 GHz) bidirectional transceiver is demonstrated in a 0.12-$mu{hbox{m}}$ SiGe BiCMOS technology. The RF front-end design eliminates the need for transmit/receive switches by demonstrating a novel PA/LNA circuit. The transceiver has a transmit conversion gain of 35 dB with a 3-${hbox{dB}}$ bandwidth of 4 GHz. The OP1dB is 8.5 dBm and Psat is 9.5 dBm. The transceiver has a receive conversion gain of 34 dB with a 3-${hbox{dB}}$ bandwidth of 3 GHz. The noise figure is 4.7 dB and OP1dB is $-$ 5 dBm at 43 GHz. The chip consumes 119.4 mW when transmitting and 54 mW when receiving, and overall chip size is 1.6 mm$times $ 0.8 mm including pads. To the author's knowledge, this work represents the first switchless millimeter-wave bidirectional transceiver in a CMOS or BiCMOS process.]]> 47 2 368 380 3139 $mu{hbox{m}}$ CMOS technology. The prototype achieves a maximum conversion gain of 44.5 dB, NF of 4.3 dB, in-channel OIP3 of 20 dBV while consuming 2.2 mA in each of the quadrature paths from a 1.8 V supply. This performance is achieved without the use of integrated inductors, which allows for a small die area of 0.5 mm$ ^{2}$.]]> 47 2 381 391 2596 ${-}$60 dBc. The power consumption including the LTA is 144 mW at a 1.8 V supply and the chip area is 1.43 mm$^{2}$ .]]> 47 2 392 406 3670 47 2 407 420 3284 ${pm}$44 ppm, approximately 14 bits of resolution, and an average step size of 0.005 ppm. All signals connecting externally to I/O pins are sine waves for reducing noise, interference, and spurs couplings. The 26 MHz DCXO fabricated in 65 nm CMOS achieves a phase noise of ${-}$149.1 dBc/Hz at 10 kHz offset measured at the sine wave buffer output. The DCXO is capable of meeting the stringent phase noise requirements for IEEE 802.11n 5 GHz WLAN devices. A typical frequency pulling of 0.01 ppm due to turning on/off the sine wave buffer is measured. The DCXO dissipates 1.2 mA of current, whereas each sine wave output buffer draws 1.4 mA. The DXCO occupies a total silicon area of 0.15 mm$^{2}$ .]]> 47 2 421 434 2500 47 2 435 443 2231 $^{2}$ in a standard 1P6M 1.8 V 0.18 $mu$m CMOS process. Measured performance achieves ${>}$61 dB spurious-free dynamic range (SFDR) in the Nyquist bandwidth with 500 MS/s, while its active area is less than one-tenth of that required by state-of-the-art 10-bit current steering DACs. To the best of our knowledge, the proposed RRBS implements the smallest area for high-speed current-steering DACs up to now. Its SFDR is also comparable to that of 12-bit published designs. Three popular figures-of-merit (FOMs) are used to compare this design with other state-of-the-art 10–12-bit DACs, with the proposed design performing best with 2 FOMs.]]> 47 2 444 453 2399 $mu$ m CMOS process was designed for direct battery hookup in a mobile application. A class-D amplifier for direct battery hookup must have a sufficiently high power supply rejection ratio (PSRR) in preparation for noise, such as when a global system for mobile communications (GSM) bursts ripples through the system power line. This amplifier has a high PSRR of 88 dB for 217-Hz power supply ripples, using a third-order loop filter. System performance and stability are improved by applying the design technique of input-feedforward delta-sigma $(DeltaSigma)$ modulators to the pulse-width modulation (PWM) class-D amplifier. A filterless method that can remove the external LC filter is employed, which offers great advantages in terms of PCB space and system cost. This amplifier achieves a power efficiency of 85.5% while delivering an output power of 750 mW into an 8-$Omega$ load from a 3.7-V supply voltage. Maximum achieved output power at 1% total harmonic distortion plus noise (THD+N) from a 4.9-V supply voltage into an 8-$Omega$ load is 1.15 W. This class-D amplifier is designed to have a broad operational range of 2.7–4.9 V for the direct use of mobile phone battery power. It has a total area of 1.01 mm$^2$ and achieves a THD+N of 0.018%.]]> 47 2 454 463 2016 $1/f$ noise, and the resulting ripple caused by the up-modulated offset and $1/f$ noise is suppressed by a ripple reduction loop. A multi-path architecture is used to eliminate the transfer function notch that would otherwise be introduced by the ripple reduction loop. The amplifier is implemented in a standard 0.7 $mu{hbox{m}}$ CMOS technology and draws 143 $muhbox{A}$ current from a 5 V supply. Its input-referred noise is 21 nV/$surd$Hz and its residual offset is less than 2$ muhbox{V}$ (12 samples). The instrumentation amplifier can also be configured as a general-purpose opamp with half the noise and offset, but which dissipates the same amount of power.]]> 47 2 464 475 2670 $mu$ m standard CMOS process demonstrate that the IC consumes less than 90 nA in the self-powering mode and less than 200 $mu$W of power in the RF-powering mode with an interrogation distance up to 40 mm. By combining self-powering and RF-powering, we show that the sensor experiences minimum down-time and can continuously monitor and record level-crossing statistics of different attributes of sensor signals.]]> 47 2 476 489 2370 $times$ 5 RTC FPAA testchip was implemented in 0.35- $mu{hbox {m}}$ CMOS technology. A set of various circuit primitives, such as one- and four-quadrant multipliers, an Euclidean distance operator and a fourth-order log-domain filter, were mapped on the chip in order to demonstrate the versatility of the approach. FPAA bandwidth reaches 20 MHz with a power consumption of 30 $muhbox{W/TE}$ and precision errors below 3%.]]> 47 2 490 503 966 $muhbox{m}$ CMOS process and extensive experimental results are provided. The Convolution Processor has also been combined with an Event-Driven Dynamic Vision Sensor (DVS) for high-speed recognition examples. The chip can discriminate propellers rotating at 2 k revolutions per second, detect symbols on a 52 card deck when browsing all cards in 410 ms, or detect and follow the center of a phosphor oscilloscope trace rotating at 5 KHz.]]> 47 2 504 517 2841 $sim$ 8% of kernel instructions so that a partial special function unit (PSFU) is implemented instead of a large dedicated SFU. The access conflicts with a look-up table (LUT) caused by concurrent accesses of twelve SPEs are reduced by a table loader (TBLD). The TBLD monitors concurrent requests from twelve SPEs and reduces an access count to LUT by distributing a coefficient to multiple SPEs with only one read-access to LUT. MRTP with area of $4times 4 {hbox{mm}}^{2}$ has been fabricated in 0.13 $mu{hbox{m}}$ CMOS technology. MRTP achieves a peak performance of 673 K rays per second while consuming 156 mW at 100 MHz with ${rm V}_{rm DD}=1.2 {rm V}$ .]]> 47 2 518 535 4714 $^{2}$ /Mb macro density and provides large-capacity on-chip page buffers and data caches for NAND flash memories to enhance their performances. A 32 KB DRAM buffer macro with 1.5 $mu{hbox{m}}^{2}$ cell has been fabricated with a 32 nm NAND flash memory process. Even with small 3 fF cell using a planar MOS capacitor, an enough ${pm}$100 mV cell signal has been obtained by introducing a technique to self-boost cell node up to 4 V using a merit of high-voltage NAND flash process, and two techniques to curtail parasitic bitline capacitance down to 60 fF at 128 wordlines per bitline. An undershoot problem of cell nodes due to unwanted plateline bounce is resolved by a two-step-rise/fall wordline scheme. Installation of dummy cell scheme to obtain a half of “1” data (not an average of “1” and “0” data) cuts out 32 KB macro size by 1.3% while suppressing mismatch to 3 mV at the grounded bitline precharge. The 32 KB test vehicle shows 90 ns random cycle time with 15 ns burst cycle time (66 Mb/s/pin). The measured characteristics of 2$,times,{hbox{10}}^{-18}$ bit error rater (BER) by soft error and 10 ms data retention at 85$,^{circ}{hbox{C}}$ are enough for page buffer application in a NAND flash memory. The measured active current of 32 KB macro is 7 mA at 90 ns random cycle, but only 3.2 mA at practical use of 15 ns burst with 256B page access.]]> 47 2 536 546 2381 $,^{circ}{hbox{C}}$. The measured refresh period at a 99.9% bit yield condition was 110 $muhbox{s}$ which is comparable to that of recently published 1T1C eDRAM designs.]]> 47 2 547 559 2715 47 2 560 573 2532 $mu{hbox{m}}$ CMOS process. The compensation is performed by using only poly-silicon resistors. This is achieved by using a second Op-amp that generates a CTAT current, which is subsequently used to enhance the curvature compensation method. The performance of the circuit was verified experimentally. Measured results have shown temperature coefficients as low as 3.9 ${hbox{ppm/}}^{circ}{hbox{C}}$ over a temperature range of 165$,^{circ}{hbox{C}}$ ( ${-}{hbox{15}},^{circ}{hbox{C}}$ to 150$,^{circ}{hbox{C}}$ ) and temperature coefficients as low as 13.7 ${hbox{ppm/}}^{circ}{hbox{C}}$ over an extended temperature range of 200$,^{circ}{hbox{C}}$ ($-hbox{50},^{circ}{hbox{C}}$ to 150$,^{circ}{hbox{C}}$ ). In addition the circuit demonstrated very good line regulation performance for a broad range of supply voltages. The measured line regulation at room temperature is 0.039% V.]]> 47 2 574 581 1276 47 2 582 582 1585 47 2 583 583 887 47 2 584 584 205 47 2 C3 C3 30