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TOC Alert for Publication# 4 2016June 27<![CDATA[Table of contents]]>517C1C4232<![CDATA[IEEE JOURNAL OF SOLID-STATE CIRCUITS]]>517C2C285<![CDATA[Table of contents]]>51715091510246<![CDATA[Introduction to the Special Issue on the 41st European Solid-State Circuits Conference (ESSCIRC)]]>51715111513869<![CDATA[Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time]]>$mu$ s to several hundred $mu$ s, and total computational energy from a fraction of 1 nJ to hundreds of nJ, depending on equation details. Very significant advantages are observed in computational speed and energy (over two orders of magnitude and over one order of magnitude, respectively) compared to those obtained with a modern microcontroller for the same RMS error.]]>517151415244589<![CDATA[A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation]]>$-9;text{dB}$ to $13;text{dB}$ with a linear-in-dB gain control feature is presented in this work. As the gain is changed, the phase shift over the entire 10–14.4 GHz bandwidth varies as little as $leq$ 2° due to a compensation circuitry that reduces the input-output phase shift sensitivity to gain variations in a robust manner with respect to temperature changes. Such a reduced phase shift variation is particularly useful to simplify the signal phase/amplitude control for the various paths of a phased array system, and allows to implement ultra-low sidelobe phased arrays. The VGA prototypes, implemented in a SiGe bipolar technology, show a noise figure of 5.1 dB, an IIP3 of $- 3;{rm dBm}$, a ${P_{1{rm dB}}}$ of $- 17; text{dBm}$, and a power consumption of 83 mW.]]>517152515362689<![CDATA[Class-C PA-VCO Cell for FSK and GFSK Transmitters]]>$0.13~mu text{m}$ CMOS technology, occupies an active area of 0.2 mm^{2}. A maximum TX efficiency of 17.5% is achieved while the TX is delivering an output power of −1 dBm at 2.45 GHz. A phase noise of −129 dBc/Hz at 2.5 MHz frequency offset results in a carrier-frequency drift below 7 Hz/s and an FSK error below 0.7%, which allows the transmitter to operate in open-loop while delivering long data-packets. The transmitter is also compliant to BLE specifications when FSK and GFSK modulations with index of 0.5 are applied.]]>517153715461876<![CDATA[A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm]]>2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode.]]>517154715658847<![CDATA[A 65 nm CMOS Wideband Radio Receiver With <inline-formula><tex-math notation="LaTeX">$Delta Sigma $</tex-math></inline-formula>-Based A/D-Converting Channel-Select Filters]]>$Delta Sigma $-based A/D-converting channel-select filters (ADCSFs). The output of the quadrature passive mixer is directly connected to the input of the ADCSFs, where a first-order $Delta Sigma $ modulator is incorporated into a fourth-order Butterworth channel-select filter (CSF) to provide sufficient dynamic range for a cellular system. A design methodology for the ADCSF is derived, where the transfer function of the CSF is preserved. The 65 nm CMOS receiver has a frequency range of 0.6–3.0 GHz and can be programmed to support the 2xLTE20, LTE20, and LTE10 bandwidths. The receiver noise figure varies from 2.3 to 3.9 dB, with a current consumption in 2xLTE20 mode between 33 mA at 0.6 GHz and 44 mA at 3.0 GHz from a 1.2 V supply, including 10–21 mA for LO phase generation and distribution. The SNDR is 47–51 dB at an LO frequency of 1.8 GHz.]]>517156615782782<![CDATA[Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication]]>$-20.7;text{dB}$ EVM for QPSK modulation without RF-DAC predistortion. The corresponding 16-QAM values are: 7.2 dBm average output power with 19.8% efficiency at $-16.5;text{dB}$ EVM. With predistortion, a QPSK modulated output achieves 5.3 dBm average power with 15.3% efficiency at $-23.6;text{dB}$ EVM, while 3.6 dBm average power with 11.6% efficiency at $-18.1;text{dB}$ EVM is realized for 16-QAM. For a sampling rate of 10 GS/s, the TX data rates are 3.33 Gb/and 6.67 Gb/s for QPSK and 16-QAM, respectively. Implemented in 40 nm bulk-CMOS, the core circuit occupies $0.18text{mm}^{2}$ core of the $2.38text{mm}^{2}$ total die area, and consumes 40.2 mW from a 0.9 V supply.]]>517157915925512<![CDATA[A 150 kHz–80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS]]>$mathrm {g}_{mathrm {m}}$ is converted to current, which is integrated on a 5th-order DT infinite-impulse response (IIR) low-pass filter with a bandwidth ranging from 150 kHz to 80 MHz. The IIR is followed by a DT amplifier which integrates selected samples to implement active finite-impulse-response (FIR) filtering while simultaneously offering variable-gain amplification. This integration happens on the DAC capacitance of a 2x interleaved 10 bit successive approximation (SAR) ADC, which finally quantizes the filtered signal at a maximum rate of 300 MS/s. The 28 nm prototype achieves +10 dBm IIP_{3}, 2 nV/$surd $ Hz input-referred noise and 52 dB gain range while consuming a maximum power of 15 mW.]]>517159316063694<![CDATA[A 106 dB A-Weighted DR Low-Power Continuous-Time <inline-formula><tex-math notation="LaTeX">$Sigma Delta $</tex-math></inline-formula> Modulator for MEMS Microphones]]>$Sigma Delta $ modulator for MEMS microphones front-end. The $Sigma Delta $ modulator 3rd-order loop filter has been implemented with a low-noise, power-optimized active-RC architecture that uses only two operational amplifiers. This solution, along with the use of a 15-level quantizer and of a feedback DAC with three-level current-steering elements, which minimizes the noise contribution for small input signals, allows achieving a DR larger than 100 dB, while consuming less than 0.5 mW, as required in always-running audio modules for portable devices. The proposed $Sigma Delta $ modulator, realized in $0.16;upmu text{m}$ CMOS technology with an area of $0.21;text{mm}^{2}$, achieves 106 dB A-weighted DR and 91.3 dB peak SNDR, consuming $390;upmu text{W}$ from a 1.6 V power supply.]]>517160716183814<![CDATA[Design of Continuous-Time <inline-formula><tex-math notation="LaTeX">$Delta Sigma $</tex-math></inline-formula> Modulators With Dual Switched-Capacitor Return-to-Zero DACs]]>$0.18;mutext{m}$ CMOS process, the modulator dissipates 14.8 mW from a 1.8 V supply.]]>517161916292706<![CDATA[A Fractional-<italic>N</italic> Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB]]>$N$ sub-sampling PLL architecture based on pipelined phase-interpolator and Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined phase-interpolator and DTC enables efficient design of the multi-phase generation mechanism required for the fractional operation. This technique can be used for designing a fractional-$N$ PLL with low in-band phase noise and low spurious tones with low power consumption. The short-current-free pipelined phase-interpolator used in this work is capable of achieving high-linearity with low-power while minimizing the intrinsic jitter. A number of other circuit techniques and layout techniques are also employed in this design for ensuring high-performance operation with minimal chip area and power consumption. The proposed fractional-$N$ PLL is implemented in standard 65 nm CMOS technology. The PLL has an operating range of 600 MHz from 4.34 GHz to 4.94 GHz. In fractional-$N$ mode, the proposed PLL achieves -249.5 dB FoM and less than -59 dBc fractional spurs.]]>517163016404470<![CDATA[12.5 Gb/s Optical Driver and Receiver ICs With Double-Threshold AGC for SATA Out-of-Band Transmission]]>517164116503984<![CDATA[A <inline-formula><tex-math notation="LaTeX">$3times 60;text{Gb/s}$</tex-math></inline-formula> Transmitter/Repeater Front-End With <inline-formula><tex-math notation="LaTeX">$4.3;{rm V}_{rm PP}$</tex-math></inline-formula> Single-Ended Output Swing in a 28nm UTBB FD-SOI Technology]]>$_{rm PP}$ with a measured input sensitivity of 10 mV$_{rm PP}$ at 40 Gb/s, and requires at least 40mV$_{rm PP}$ input signal level to fully saturate the output driver for maximum swing operation at 60 Gb/s. Scaled, cascaded single-ended CMOS inverter transimpedance amplifiers with resistive and inductive feedback and interstage series inductive peaking were used to form the preamplifiers of each lane. These were optimized for maximum bandwidth and large gain, and drive the > 4V$_{rm PP}$ swing series-stacked cascoded CMOS inverter output stage. The single-ended CMOS-inverter topologies ensure that the total power consumption scales with the data rate and reduce the lane footprint to that of a ground-signal pad I/O. The measured lane-to-lane isolation is better than 40 dB up to 55 GHz, while the measured Tx-to-Rx dynamic range, defined as the ratio of the maximum output swing and corresponding minimum input voltage and sensitivity, is larger than 54 dB up to 40 Gb/s.]]>517165116625191<![CDATA[Optical Wireless APD Receiver With High Background-Light Immunity for Increased Communication Distances]]>−9 is received with a sensitivity of −31.8 dBm. The second receiver consists of two pn-photodiodes connected to a highly sensitive differential transimpedance amplifier with a nonlinear feedback. This circuit is capable of detecting light power differences down to −90 dBm and is implemented two times. Its purpose is the detection of the light spot’s position on the receiver. The complete chip is fabricated in a standard high-voltage $0.35~mu text{m}$ CMOS technology. The performance in a wireless communication scenario with strong background irradiance is explored, and a comparison with published optoelectronic integrated receivers is given.]]>517166316732429<![CDATA[A 13.2 b Optical Proximity Sensor System With 130 klx Ambient Light Rejection Capable of Heart Rate and Blood Oximetry Monitoring]]>517167416832300<![CDATA[Integrated Fluxgate Magnetometer for Use in Isolated Current Sensing]]>517168416942803<![CDATA[<inline-formula> <tex-math notation="LaTeX">$mu $ </tex-math></inline-formula>RNG: A 300–950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS]]>$mu $ RNG, an ultra-lightweight all-digital full-entropy true-random number generator (TRNG), fabricated in 14 nm high-k/metal-gate FinFET CMOS, targeted for on-die generation of cryptographic keys in energy-constrained IoT and wearable platforms. The $mu $ RNG combines the entropy of multiple independent sources to generate an output bitstream that is indistinguishable from an ideal unbiased entropy source. Three independent self-calibrating all-digital entropy sources, coupled with XOR feedback shift-register based correlation suppressors and an in-line compact Barak–Impagliazzo–Wigderson (BIW) extractor enable ultra-low energy consumption of 3 pJ/full-entropy bit with a dense layout occupying 1008 $mu text{m}^{2}$ , while achieving: (i) 162.5 Mbps full-entropy throughput at 1.3 GHz operation, with total power consumption of 1.5 mW and leakage power component of 90 $mu text{W}$ , measured at 0.75 V, 25 °C, (ii) mutually uncorrelated raw bitstreams from the three entropy sources with phi-coefficient cross-correlation <0.003, (iii) extracted full-entropy bitstream that passes all 16 NIST RNG tests with measured Shannon entropy up to 0.9999999995, and lower-bound min-entropy $mathrm {H}_{infty }> 0.99$ , (iv) hysteresis-free extracted output for lags 1–1000, with ACF ${sim }0$ within 95% confidence bounds of a Gaussian distribution $(mu =0,sigma ^{2}=0.002)$ , (v) wide operating supply volta-
e range of 300–950 mV with throughput scaling to 225 Mbps at 950 mV and robust sub-threshold voltage performance of 400 Kbps, $4~mu text{W}$ , measured at 300 mV, 25 °C, (vi) peak energy-efficiency of 323 Gbps/W at near-threshold voltage of 400 mV, with full-entropy throughput of 8.6 Mbps, total power consumption of $27~mu text{W}$ , (vii) $6.5times $ reduction in gate count and $5.4times $ lower energy consumption compared to conventional AES-based entropy extractors.]]>517169517044267<![CDATA[An 18 V Input 10 MHz Buck Converter With 125 ps Mixed-Signal Dead Time Control]]>${ > } 18,text{V}$ with 10 MHz switching frequency is presented. A high resolution dead time of ${sim} 125,text{ps}$ allows to reduce dead time dependent losses without requiring body diode conduction to evaluate the dead time. High resolution is achieved by frequency compensated sampling of the switching node and by an 8 bit differential delay chain. Dead time parameters are derived in a comprehensive study of dead time depended losses. This way, the efficiency of fast switching DCDC converters can be optimized by eliminating the body diode forward conduction losses, minimizing reverse recovery losses and by achieving zero voltage switching. High-speed circuit blocks for fast switching operation are presented including level shifter, gate driver, PWM generator. The converter has been implemented in a 180 nm high-voltage BiCMOS technology. The power losses were measured to be reduced by up to 31% by the proposed dead time control, which results in a 5.3% efficiency increase at ${V_{rm IN} = } 18,text{V}$, ${V_{rm OUT} = } 5,text{V}$, and 0.45 A load. At ${V_{rm IN} = }12,text{V}$, the peak efficiency is 81.2% with an efficiency improvement of 6% with dead time control.]]>517170517152846<![CDATA[Fully Integrated Startup at 70 mV of Boost Converters for Thermoelectric Energy Harvesting]]>$40~Omega $ , an output power of $17~ {mu }text{W}$ can be provided, which translates to an end-to-end efficiency of 58%. The converter employs Schmitt-trigger logic startup control circuitry and an ultra-low voltage charge pump using modified Schmitt-trigger driving circuits optimized for driving capacitive loads. Together with a novel ultra-low leakage power switch and the required control scheme, to the best of the authors’ knowledge, this enables the lowest minimum voltage with fully integrated startup.]]>517171617262286<![CDATA[2016 IEEE Compound Semiconductor IC Symposium]]>517172717271311<![CDATA[Introducing IEEE Collabratec]]>517172817282132<![CDATA[Information For Authors]]>517C3C389