http://ieeexplore.ieee.org TOC Alert for Publication# 4 2013 May 16 48 5 C1 C4 144 48 5 C2 C2 146 48 5 1109 1110 143 48 5 1111 1112 256 $f_{T}/f_{MAX}$ of 240/270 GHz. Each chip comprises four phased array elements with distributed calibration memory and calibrated direct up- and down-conversion mixer chain. Each receive channel has a conversion gain of 33 dB and noise figure of < 7 dB from 75–95 GHz. Each transmit channel has a flat saturated output power of > 5 dBm between 70 and 100 GHz. Both transmitter and receiver arrays operate from 1.5 V and 2.5 V power supplies and consume 1 W each. Using a die-on-PCB prototype with integrated antennas, a wireless link operating at 10 Gb/s (using 16-QAM) or 8.75 Gb/s (using 32-QAM) is demonstrated at a distance of 1-meter with a carrier frequency of 88 GHz.]]> 48 5 1113 1125 3074 48 5 1126 1137 3477 $-$ 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 1500 measurements of the PLL across PVT variations were taken, further validating the proposed design. Phase noise variation across 55 dies for four different frequencies is $sigma<hbox{ 0.6 dB}$ . Also, phase noise variation across supply voltages of 0.7–1.5 V is 2 dB and across 60$^{circ}{rm C}$ temperature variation is 3 dB. At the 25 GHz center frequency, the VCO $FOM_{T}$ is 188 dBc/Hz. Additionally, a digitally assisted autonomic biasing technique is implemented in the PLL to provide a phase noise and power optimized VCO bias across frequency and process. Measurement results indicate the efficacy of the autonomic biasing scheme.]]> 48 5 1138 1150 3425 48 5 1151 1160 2354 $-$ 110 dBm, an IIP3 of $-$ 9.5 dBm, and a calibrated image rejection ratio of 65 dBc, while consuming 61 mA. The polar transmitter architecture is chosen for its SAW-less TX capability, smaller area, and low current consumption. It achieves an ORFS (output radio frequency spectrum) of $-$68 dB and $-$64 dB at 400 kHz in GMSK and EDGE mode, respectively, while consuming 61 mA. The loop gain normalization, dc offset and AM/PM delay of the polar system are compensated to be better than 1% error, 1 mV, and 1.9 ns within 170 $mu$s, respectively. Several techniques are employed to minimize interference coupling within the SoC; these include frequency planning, circuit implementation, transceiver architecture optimization, and digital clock selection. The measured sensitivity and the output spectrum of the three wireless systems under full-feature phone operation are virtually unchanged.]]> 48 5 1161 1173 3438 ${rm N}+1/{rm N}+2$ performance of 24/29 dB. A harmonic rejection mixer (HRM) with a tracking filter (TF) scheme employing three external inductors, one for each TV band, achieves better than 78/83-dB harmonic-rejection for the VHFI/VHFIII bands. A single LC-tank VCO with a programmable divider that has a 50% duty cycle correction scheme covers the entire TV band with accurate LO phases. A digital automatic gain control (AGC) scheme detects the presence of ACI and/or GSM burst-mode blockers through an RF wideband peak detector (WBPD) and adjusts the receiver gain for optimum dynamic range. The RF tuner is fabricated in 65-nm CMOS technology with silicon area of only 1.25 $hbox{mm}^{2}$ and draws 37/19 mA for analog TV and FM radio receiver modes, respectively.]]> 48 5 1174 1187 3490 34 dB. The receiver consumes 10–12 mW (including VCOs, pulse generation and baseband) over a frequency range of 0.7–3.2 GHz with a 1.3 V supply.]]> 48 5 1188 1198 1808 48 5 1199 1211 3280 48 5 1212 1224 3351 $pm$ 0.8 dB.]]> 48 5 1225 1236 2022 $({V}_{{t}1})$ range of $Delta{V}_{{t}1}sim hbox{ 2 V}$, very fast response $({t}_{1})$ to ESD transients of rising time ${t}_{r}sim hbox{ 100 pS}$ and pulse duration ${t}_{d}sim hbox{ 1 nS}$, ESD protection capability $({I}_{{t}2})$ of at least 25 $hbox{mA}/muhbox{m}$ for human body model (HBM) and 400 $hbox{mA}/muhbox{m}$ for charged device model (CDM) equivalent stressing, and very low leakage current $({I}_{rm leak})$ as low as 1.2 pA. Field-programmable ESD protection circuit design examples are discussed.]]> 48 5 1237 1249 2972 ${pm} $450 kHz (${pm} $180 ppm), and an ACR of 40 dB are achieved for a MI of 2.]]> 48 5 1250 1263 3357 $sqrt{rm Hz}$ average input-referred noise current spectral density. Total chip power including output buffering is 28.2 mW from a 2.5 V supply, with the core TIA consuming 8.2 mW, and the chip area including pads is 960 µm x 780 µm.]]> 48 5 1264 1275 2631 ${rm mV}_{rm ppd}$ using a low-voltage pseudo-differential regulator that employs a partial negative-resistance load for improved low frequency gain. 1:8 input de-multiplexing is performed at the receiver equalizer output with 8 parallel input samplers clocked from an 8-phase injection-locked oscillator that provides more than 1UI de-skew range. In the transmitter clocking circuitry, per-phase duty-cycle and phase-spacing adjustment is implemented to allow adequate timing margins at low operating voltages. Fabricated in a general purpose 65 nm CMOS process, the transceiver achieves 4.8–8 Gb/s at 0.47–0.66 pJ/b energy efficiency for ${rm V}_{rm DD}=0.6$–0.8 V.]]> 48 5 1276 1289 2559 $^{2}$ ) with 84 dB of dynamic range and an input referred noise of 49 nT/$surd$Hz. Performance is demonstrated through detection of an ovarian cancer biomarker, secretory leukocyte peptidase inhibitor (SLPI), spiked at concentrations as low as 10 fM. This system is designed as a replacement for optical protein microarrays while also providing real-time kinetics monitoring.]]> 48 5 1290 1301 1928 48 5 1302 1314 3072 ${rm Cu}_{rm x}{rm Si}_{rm y}{rm O}$ resistive random access memory (ReRAM) test macro with $20{rm F}^{2}$ cell size is developed based on logic process for embedded applications. Smart and adaptive write and read assist circuits are proposed to fix yield and power consumption issues arising from large variations in set/reset time and high-temperature cell resistance. Self-adaptive write mode (SAWM) helps increase the ${rm R}_{rm off}/{rm R}_{rm on}$ window from 8X to 24X at room temperature. The reset bit yield is improved from 61.5% to 100% and the high power consumption is eliminated after the cell switches to ${rm R}_{rm on}$ during set. Self-adaptive read mode (SARM) increases read bit yield from 98% to 100% at 125$^{circ}{rm C}$. The typical access time of the on-pitch voltage sense amplifier (SA) is 21 ns. High bandwidth throughput is supported.]]> 48 5 1315 1322 2282 48 5 1323 1323 847 48 5 1324 1324 871 48 5 C3 C3 101