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TOC Alert for Publication# 4 2016February 11<![CDATA[[Front cover]]]>512C1C4161<![CDATA[IEEE Journal of Solid-State Circuits publication information]]>512C2C2137<![CDATA[Table of contents]]>512321322161<![CDATA[An Ultra-Wideband IF Millimeter-Wave Receiver With a 20 GHz Channel Bandwidth Using Gain-Equalized Transformers]]>gain-equalized transformers. Receiver measurements show an overall flat bandwidth response of 20 GHz, with a total gain of 20 dB, a minimum double-sideband noise figure of 7.8 dB, and an input 1 dB compression power of while consuming 115 mW from a 1.1 V supply. The test chip, implemented in a six-metal layer 40 nm CMOS process, occupies an area (including pads) of .]]>5123233312980<![CDATA[A High IIP2 SAW-Less Superheterodyne Receiver With Multistage Harmonic Rejection]]>surface acoustic wave (SAW)-less superheterodyne receiver (RX) for 4G cellular applications. The RX operates in discrete-time domain and introduces various innovations to simultaneously improve noise and linearity performance while reducing power consumption: a highly linear wideband noise-canceling low-noise transconductance amplifier (LNTA), a blocker-resilient octal charge-sharing bandpass filter, and a cascaded harmonic rejection circuitry. The RX is implemented in 28-nm CMOS and it does not require any calibration. It features NF of 2.1–2.6 dB, an immeasurably high input second intercept point for closely-spaced or modulated interferers, and input third intercept point of 8–14 dBm, while drawing only 22–40 mW in various operating modes.]]>5123323472788<![CDATA[Mitigation of Oscillator Pulling in SoCs]]>5123483561868<![CDATA[A 2.02–5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS]]> . With a 0.4 V supply and a Nyquist rate input, the prototype consumed 200 nW at 250 kS/s and achieved an ENOB of 8.63 bits and a SFDR of 78.5 dB. The operation frequency was scalable from 250 kS/s to 4 MS/s. The converter had a power supply range of 0.4–0.7 V, and the figure of merit (FoM) were 2.02–5.16 fJ/conversion step.]]>5123573641592<![CDATA[A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC]]> time-interleaved 6-bit 5 GS/s 3 b/cycle SAR analog-to-digital converter (ADC). Hardware overhead induced by a 3 b/cycle architecture is eased by an interpolation technique where around 1/3 of the hardware is saved. In addition, complicated switching controls are simplified with a proposed fractional DAC array switching scheme, thus reducing the design complexity and the hardware burden. A boundary detection code overriding (BDCO) is introduced to reduce error probability at the large error magnitude, by utilizing the extended time when the comparator is at reset and the DAC at settling. The floorplan of the front-end is optimized for important interleaving clock distributions, and a master-clock-control bootstrapped-switch technique is adopted to suppress the timing-skew effect among the channels. The unit capacitor has been designed to suit for the DAC structure which allows top-plate sharing in both directions, plus, the offset is calibrated on-chip with a clocking variable biasing transistor pair at the latch. Measurement results show that the prototype can achieve 5 GS/s with a total power consumption of 5.5 mW at 1 V supply in 65 nm CMOS technology. Besides, it exhibits a 30.76 dB SNDR and 43.12 dB SFDR at Nyquist, which yields a Walden FoM of 39 fJ/conversion-step.]]>5123653772246<![CDATA[A Compact First-Order <inline-formula><tex-math notation="LaTeX">$SigmaDelta $</tex-math></inline-formula> Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process]]> modulator for on-die voltage measurements in such applications. The primary design focus is to achieve a highly compact area so that many instances can be integrated to cover the testing of multiple analog IPs on a single chip die. The proposed modulator deploys an inverter-based architecture which enables the aggressive area reduction. There are two new additional enhancements: 1) hardware dithering to minimize the limit-cycling effect and 2) time-multiplexed pseudodifferential operation for common mode rejection. The modulator exhibits a figure of merit (FOM) of 554.7 fJ/conv-step, in spite of the compact area of only .]]>5123783903056<![CDATA[A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC]]> and achieves a stable in-band phase noise of lower than in a wide range of supply voltage from 1 to 1.4 V.]]>5123914003393<![CDATA[A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-Time PVT Calibrator With Replica-Delay Cells]]> and the power consumption was 3.6 mW.]]>5124014113451<![CDATA[A 6.7 MHz to 1.24 GHz <inline-formula><tex-math notation="LaTeX">$text{0.0318};{text{mm}^{text{2}}}$</tex-math></inline-formula> Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS]]> . The measured peak-to-peak and root-mean-square jitter at 1.24 GHz are 2.22 ps and 424.62 fs, respectively. The ADDLL consumes 14.5 mW while operating at 1.24 GHz.]]>5124124276361<![CDATA[A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition]]> ) from 4 to 10.5 Gb/s with pseudorandom binary sequence (PRBS) data sequences ranging from PRBS7 to PRBS31. The proposed automatic frequency acquisition scheme always locks the CDR loop within 1000 ppm residual frequency error in worst case. At 10 Gb/s, the CDR consumes 22.5 power and achieves a recovered clock long-term jitter of 2.2 /24.0 with PRBS31 input data. The measured JTRAN bandwidth and JTOL corner frequencies are 0.2 and 9 MHz, respectively.]]>5124284395864<![CDATA[A 10 Gb/s Inductorless AGC Amplifier With 40 dB Linear Variable Gain Control in 0.13 <inline-formula><tex-math notation="LaTeX">$upmu text{m}$</tex-math></inline-formula> CMOS]]> with better than gain error. The relationship between tuning range and approximation error is analyzed and a novel current ratio generator circuit is proposed to implement the approximation functions in the current domain. The AGC circuit achieves a highest data rate of 10 Gb/s for PRBS input, maintaining constant differential output with a BER for an input dynamic range of (15–240 ). Fabricated in IBM 0.13 CMOS technology, the chip draws 50 mW from a 1.2 V power supply (excluding the output buffer) and occupies an active area of .]]>5124404565117<![CDATA[Oscillator-Based Reactance Sensors With Injection Locking for High-Throughput Flow Cytometry Using Microwave Dielectric Spectroscopy]]> of noise sensitivity at 100 kHz filtering bandwidth, enabling measurement throughput exceeding 1 k cells/s. The sensor prototype is implemented in 65 nm CMOS technology and consumes 65 mW at 1 V supply.]]>5124574727075<![CDATA[A 4.7 T/11.1 T NMR Compliant 50 nW Wirelessly Programmable Implant for Bioartificial Pancreas <italic>In Vivo</italic> Monitoring]]>5124734832345<![CDATA[Time-Divided Spread-Spectrum Code-Based 400 fW-Detectable Multichannel fNIRS IC for Portable Functional Brain Imaging]]>5124844954560<![CDATA[Variation-Tolerant Quick-Start-Up CMOS Crystal Oscillator With Chirp Injection and Negative Resistance Booster]]> . A new analysis of the proposed CI and NRB clarifies the validity of the universal optimum control method. It explains the reason why the proposed CI and NRB reduce the start-up time and its variation. The proposed crystal oscillator with the proposed CI and NRB exhibits a start-up time of 158 μs at 39.25 MHz. The variation of the start-up time variations is over the supply voltage range of 1.2–1.8 V and over the temperature range of . The power consumption of the crystal oscillator in the steady state is 181 μW with a phase noise of at 1 kHz offset frequency, which corresponds to a figure of merit (FoM) of 276 dB.]]>5124965081966<![CDATA[A 5.58 nW Crystal Oscillator Using Pulsed Driver for Real-Time Clocks]]>on-resistance necessary for reliable operation. The different supply levels are generated on-chip by a switched capacitor network (SCN) from a single supply. The circuit has been tested at different supply voltages and temperatures. It shows a minimum power consumption of 5.58 nW and power supply sensitivity of 30.3 ppm/V over supply voltage of 0.94–1.2 V, without degrading the crystal’s temperature dependency: between . Moreover, its performance as a real-time clock has been verified by measurement of an Allan deviation of .]]>5125095222384<![CDATA[A 50 nW-to-10 mW Output Power Tri-Mode Digital Buck Converter With Self-Tracking Zero Current Detection for Photovoltaic Energy Harvesting]]> CMOS technology for photovoltaic energy harvesting. The on-chip gate-boosted digital pulsewidth modulation (DPWM) improves the conversion efficiency at heavy load conditions. Pulse–frequency modulation (PFM) along with digital self-tracking zero current detection is proposed to avoid reverse current at light load. The asynchronous mode (AM) operation further reduces the controller loss and improves the conversion efficiency at ultra-light load conditions. By applying DPWM, PFM, and AM at different load conditions, the proposed converter provides a maximum conversion efficiency of 92% with output power ranging from 50 nW to 10 mW. In addition, the proposed buck converter achieves more than 70% efficiency from 400 nW to 10 mW output power.]]>5125235322258<![CDATA[An Efficiency-Enhanced Hybrid Supply Modulator With Single-Capacitor Current-Integration Control]]> sinusoidal signal with high fidelity up to 10 MHz. The measured output voltage ripple is reduced to below 8 mV. The peak conversion efficiency is 88.3% at the maximum output power of 23 dBm.]]>5125335422223<![CDATA[A Successive-Approximation Switched-Capacitor DC–DC Converter With Resolution of <inline-formula><tex-math notation="LaTeX">$V_{text{IN}}/{2^N}$</tex-math></inline-formula> for a Wide Range of Input and Output Voltages]]> , where is the input voltage and is the number of stages. As the SAR SC converter generates the output voltage through SAR, each stage of 2:1 SC converter provides a fixed voltage level, requiring minimal configuration change for regulation. Analysis shows that the SAR SC converter has a slow-switching-limit output impedance increasing proportionally to (number of resolution), and switching loss of bottom-plate parasitic capacitor decreasing with the number of stages. As a test chip, an SAR SC converter with 7 b resolution is fabricated in 180 nm CMOS process and implemented by cascading 4:1 and five 2:1 two-phase interleaving SC stages. It achieves 31.25 mV voltage resolution with output voltages over 0.4 V at . Using this fine grain voltage regulation approach, line and load regulations are implemented with a feedback/feedforward controller with peak efficiency of 72% for load currents from . The test chip occupies and utilizes on-chip capacitors of 2.24 nF in t-
tal.]]>5125435564210<![CDATA[A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation]]> collapse schemes in an efficient way to maximize improvements while saving on area and energy overhead of these assists. Relative delay and pulse width of assist control signals are also designed with configurability to provide tuning of assist strengths. Sense-amplifier offset compensation scheme uses capacitors to store and negate threshold mismatch of input transistors. A test chip fabricated in 28 nm HP CMOS process demonstrates operation down to 0.5 V with write assists and more than 10% reduction in word-line pulsewidth with the offset compensated sense amplifiers.]]>5125575672713<![CDATA[2016 IEEE Compound Semiconductor IC Symposium]]>5125685681163<![CDATA[IEEE Journal of Solid-State Circuits information for authors]]>512C3C3107