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TOC Alert for Publication# 2192 2007November 26<![CDATA[Ant colony optimisation for task matching and scheduling]]>1536373380194<![CDATA[Two-phase prediction of L1 data cache misses]]>1536381388264<![CDATA[LSQ: a power efficient and scalable implementation]]>1536389398300<![CDATA[Efficient new approach for modulo 2/sup n/-1 addition in RNS]]>n-1 addition algorithm is presented, which is applicable in the residue number system. In contrast to previous work, the input carry in the first stage of the addition is set to one. The associated output carry is then used to conditionally modify the sum to produce the correct modulo 2^{n}-1 result. Moreover, unlike recent adders in the literature, the result never exceeds the dynamic range of the modulus. Actual VLSI implementations using 130 nm standard-cell technology show that the corresponding architectures provide improved trade-offs in the power-delay-area space when compared against existing designs]]>1536399405292