<?xml version="1.0" ?>
<rss version="2.0">
	<channel>
		<title><![CDATA[ Computers, IEEE Transactions on - new TOC ]]></title>
		<link>http://ieeexplore.ieee.org</link>
		<description>TOC Alert for Publication# 12 </description>
		<year>2013</year>
		<month>May      </month>
		<day>21</day>
		<item>
			<title><![CDATA[Guest Editors' introduction: Special section on optimizing the cloud]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6509887]]></link>
			<description><![CDATA[Cloud computing is defined as a pool of virtualized computer resources. Based on this virtualization, the cloud computing paradigm allows workloads to be deployed and scaled-out quickly through the rapid provisioning of virtual machines or physical machines. A cloud computing platform supports redundant, self-recovering, highly scalable programming models that allow workloads to recover from many inevitable hardware/software failures and monitoring resource use in real time for providing physical and virtual servers, on which the applications can run. A cloud computing platform is more than a collection of computer resources, because it provides a mechanism to manage those resources. In a cloud computing platform, software is migrating from the desktop into the "clouds" of the Internet, promising users anytime, anywhere access to their programs and data. The editor-in-chief provides an overview of the technical articles and features presented in this issue.]]></description>
			<pubDate><![CDATA[June  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6509887]]></guid>
			<volume>62</volume>
			<issue>6</issue>
			<startPage>1058</startPage>
			<endPage>1059</endPage>
			<fileSize>60</fileSize>
			<authors><![CDATA[Avresky, D.R.;]]></authors>
		</item>
		<item>
			<title><![CDATA[On the Optimal Allocation of Virtual Resources in Cloud Computing Networks]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6463381]]></link>
			<description><![CDATA[Cloud computing builds upon advances on virtualization and distributed computing to support cost-efficient usage of computing resources, emphasizing on resource scalability and on demand services. Moving away from traditional data-center oriented models, distributed clouds extend over a loosely coupled federated substrate, offering enhanced communication and computational services to target end-users with quality of service (QoS) requirements, as dictated by the future Internet vision. Toward facilitating the efficient realization of such networked computing environments, computing and networking resources need to be jointly treated and optimized. This requires delivery of user-driven sets of virtual resources, dynamically allocated to actual substrate resources within networked clouds, creating the need to revisit resource mapping algorithms and tailor them to a composite virtual resource mapping problem. In this paper, toward providing a unified resource allocation framework for networked clouds, we first formulate the optimal networked cloud mapping problem as a mixed integer programming (MIP) problem, indicating objectives related to cost efficiency of the resource mapping procedure, while abiding by user requests for QoS-aware virtual resources. We subsequently propose a method for the efficient mapping of resource requests onto a shared substrate interconnecting various islands of computing resources, and adopt a heuristic methodology to address the problem. The efficiency of the proposed approach is illustrated in a simulation/emulation environment, that allows for a flexible, structured, and comparative performance evaluation. We conclude by outlining a proof-of-concept realization of our proposed schema, mounted over the European future Internet test-bed FEDERICA, a resource virtualization platform augmented with network and computing facilities.]]></description>
			<pubDate><![CDATA[June  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6463381]]></guid>
			<volume>62</volume>
			<issue>6</issue>
			<startPage>1060</startPage>
			<endPage>1071</endPage>
			<fileSize>1467</fileSize>
			<authors><![CDATA[Papagianni, Chrysa;Leivadeas, Aris;Papavassiliou, Symeon;Maglaris, Vasilis;Cervell&#x00F3;-Pastor, Cristina;Monje, &#x00C1;lvaro;]]></authors>
		</item>
		<item>
			<title><![CDATA[Workload-Based Software Rejuvenation in Cloud Systems]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6463380]]></link>
			<description><![CDATA[Cloud computing is a promising paradigm able to rationalize the use of hardware resources by means of virtualization. Virtualization allows to instantiate one or more virtual machines (VMs) on top of a single physical machine managed by a virtual machine monitor (VMM). Similarly to any other software, a VMM experiences aging and failures. Software rejuvenation is a proactive fault management technique that involves terminating an application, cleaning up the system internal state, and restarting it to prevent the occurrence of future failures. In this work, we propose a technique to model and evaluate the VMM aging process and to investigate the optimal rejuvenation policy that maximizes the VMM availability under variable workload conditions. Starting from dynamic reliability theory and adopting symbolic algebraic techniques, we investigate and compare existing time-based VMM rejuvenation policies. We also propose a time-based policy that adapts the rejuvenation timer to the VMM workload condition improving the system availability. The effectiveness of the proposed modeling technique is demonstrated through a numerical example based on a case study taken from the literature.]]></description>
			<pubDate><![CDATA[June  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6463380]]></guid>
			<volume>62</volume>
			<issue>6</issue>
			<startPage>1072</startPage>
			<endPage>1085</endPage>
			<fileSize>1286</fileSize>
			<authors><![CDATA[Bruneo, Dario;Distefano, Salvatore;Longo, Francesco;Puliafito, Antonio;Scarpa, Marco;]]></authors>
		</item>
		<item>
			<title><![CDATA[Integrated Approach to Data Center Power Management]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6463382]]></link>
			<description><![CDATA[Energy accounts for a significant fraction of the operational costs of a data center, and data center operators are increasingly interested in moving toward low-power designs. Two distinct approaches have emerged toward achieving this end: the power-proportional approach focuses on reducing disk and server power consumption, while the green data center approach focuses on reducing power consumed by support-infrastructure like cooling equipment, power distribution units, and power backup equipment. We propose an integrated approach, which combines the benefits of both. Our solution enforces power-proportionality at the granularity of a rack or even an entire containerized data center; thus, we power down not only idle IT equipment, but also their associated support-infrastructure. We show that it is practical today to design data centers to power down idle racks or containers&amp;#x2014;and in fact, current online service trends strongly enable this model. Finally, we show that our approach combines the energy savings of power-proportional and green data center approaches, while performance remains unaffected.]]></description>
			<pubDate><![CDATA[June  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6463382]]></guid>
			<volume>62</volume>
			<issue>6</issue>
			<startPage>1086</startPage>
			<endPage>1096</endPage>
			<fileSize>1109</fileSize>
			<authors><![CDATA[Ganesh, Lakshmi;Weatherspoon, Hakim;Marian, Tudor;Birman, Ken;]]></authors>
		</item>
		<item>
			<title><![CDATA[Component-Composition Graphs: (t,k)-Diagnosability and Its Application]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6165261]]></link>
			<description><![CDATA[$((t,k))$-diagnosis, which is a generalization of sequential diagnosis, requires that at least $(k)$ faulty processors should be identified and repaired in each iteration provided there are at most $(t)$ faulty processors, where $(tge k)$. In this paper, we propose a unified approach for computing the $((t,k))$-diagnosability of numerous multiprocessor systems (graphs) under the Preparata, Metze, and Chien's model, including hypercubes, crossed cubes, twisted cubes, locally twisted cubes, multiply-twisted cubes, generalized twisted cubes, recursive circulants, M&amp;#x00F6;bius cubes, Mcubes, star graphs, bubble-sort graphs, pancake graphs, and burnt pancake graphs. Our approach first sketches the common properties of the above classes of graphs, and defines a superclass of graphs, called $(m)$--dimensional component-composition graphs, to cover them. We then show that the $(m)$-dimensional component-composition graph $(G)$ for $(m ge 4)$ is $((Omega (h),kappa (G)))$-diagnosable, where $(displaystyle h={left{matrix{{2^{m-2}times lg {(m-1)}over m-1} &amp;#x0026;{rm if} 2^{m-1} le vert V(G)vert &amp;#x003C; m!cr 2^{m-2}hfill &amp;#x0026; {rm if} vert V(G)vert ge m!,hfill}right.})$ and $(kappa (G))$ and $(vert V(G)vert)$ denote the node connectivity and the number of nodes in $(G)$, respectively. Based on this result, the $((t,k))$-diagnosability of the above multiprocessor systems can be computed efficiently.]]></description>
			<pubDate><![CDATA[June  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6165261]]></guid>
			<volume>62</volume>
			<issue>6</issue>
			<startPage>1097</startPage>
			<endPage>1110</endPage>
			<fileSize>542</fileSize>
			<authors><![CDATA[Chen, Chun-An;Hsieh, Sun-Yuan;]]></authors>
		</item>
		<item>
			<title><![CDATA[Error Detection and Correction in Content Addressable Memories by Using Bloom Filters]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6158642]]></link>
			<description><![CDATA[A content addressable memory (CAM) is an SRAM-based memory that can be accessed in parallel to search for a given search word, providing as a result the address of the matching data. Like conventional memories, a CAM can be affected by the occurrence of single event upsets (SEUs) that can alter the content of one of more memory cells causing different effects such as pseudo-HIT or pseudo-MISS events. It is well known that, because of the parallel search performed by a CAM during the query of a word, a standard error correction code could not defend it against SEU events. In this paper, we propose a method that does not require any modification to a CAM's internal structure and, therefore, can be easily applied at system level. Error detection is performed by using a probabilistic structure called &#x0022;Bloom filter,&amp;#x201D; which can signal if a given data is present in the CAM. Bloom filters permit to efficiently store and query the presence of data in a set. But, while a CAM suffers from SEU induced errors, the probabilistic nature of Bloom filters has as a consequence the so called false-positive effect. This paper shows that, by combining the use of a Bloom filter with a CAM, the complementary limitations of these modules can be compensated. The combined use of a CAM and a Bloom filter is analyzed in different cases, showing that the proposed technique can be implemented with a low penalty in terms of area and power consumption.]]></description>
			<pubDate><![CDATA[June  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6158642]]></guid>
			<volume>62</volume>
			<issue>6</issue>
			<startPage>1111</startPage>
			<endPage>1126</endPage>
			<fileSize>2149</fileSize>
			<authors><![CDATA[Pontarelli, Salvatore;Ottavi, Marco;]]></authors>
		</item>
		<item>
			<title><![CDATA[Exact Worst Case TCAM Rule Expansion]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6165260]]></link>
			<description><![CDATA[In recent years, hardware-based packet classification has became an essential component in many networking devices. It often relies on ternary content-addressable memories (TCAMs), which can compare in parallel the packet header against a large set of rules. Designers of TCAMs often have to deal with unpredictable sets of rules. These result in highly variable rule expansions, and can only rely on heuristic encoding algorithms with no reasonable guarantees. In this paper, given several types of rules, we provide new upper bounds on the TCAM worst case rule expansions. In particular, we prove that a $(W)$-bit range can be encoded in $(W)$ TCAM entries, improving upon the previously known bound of $(2W-5)$. We further prove the optimality of this bound of $(W)$ for prefix encoding, using new analytical tools based on independent sets and alternating paths. Next, we generalize these lower bounds to a new class of codes called hierarchical codes that includes both binary codes and Gray codes. Last, we propose a modified TCAM architecture that can use additional logic to significantly reduce the rule expansions, both in the worst case and using real-life classification databases.]]></description>
			<pubDate><![CDATA[June  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6165260]]></guid>
			<volume>62</volume>
			<issue>6</issue>
			<startPage>1127</startPage>
			<endPage>1140</endPage>
			<fileSize>576</fileSize>
			<authors><![CDATA[Rottenstreich, Ori;Cohen, Rami;Raz, Danny;Keslassy, Isaac;]]></authors>
		</item>
		<item>
			<title><![CDATA[Exploring and Exploiting the Multilevel Parallelism Inside SSDs for Improved Performance and Endurance]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6165265]]></link>
			<description><![CDATA[Given the multilevel internal SSD parallelism at the different four levels: channel-level, chip-level, die-level, and plane-level, how to exploit these levels of parallelism will directly and significantly impact the performance and endurance of SSDs, which is in turn primarily determined by three internal factors, namely, advanced commands, allocation schemes, and the priority order of exploiting the four levels of parallelism. In this paper, we analyze these internal factors to characterize their impacts, interplay, and parallelism for the purpose of performance and endurance enhancement of SSDs through an in-depth experimental study. We come to the following key conclusions: 1) Different advanced commands provided by Flash manufacturers exploit different levels of parallelism inside SSDs, where they can either improve or degrade the SSD performance and endurance depending on how they are used; 2) Different physical-page allocation schemes employ different advanced commands and exploit different levels of parallelism inside SSDs, giving rise to different performance and endurance impacts; 3) The priority order of using the four levels of parallelism has the most significant performance and endurance impact among the three internal factors. The optimal priority order of using the four levels of parallelism in SSDs is found to be: 1) the channel-level parallelism; 2) the die-level parallelism; 3) the plane-level parallelism; and 4) the chip-level parallelism.]]></description>
			<pubDate><![CDATA[June  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6165265]]></guid>
			<volume>62</volume>
			<issue>6</issue>
			<startPage>1141</startPage>
			<endPage>1155</endPage>
			<fileSize>4598</fileSize>
			<authors><![CDATA[Hu, Yang;Jiang, Hong;Feng, Dan;Tian, Lei;Luo, Hao;Ren, Chao;]]></authors>
		</item>
		<item>
			<title><![CDATA[GPU-to-GPU and Host-to-Host Multipattern String Matching on a GPU]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6165263]]></link>
			<description><![CDATA[We develop GPU adaptations of the Aho-Corasick and multipattern Boyer-Moore string matching algorithms for the two cases GPU-to-GPU (input to the algorithms is initially in GPU memory and the output is left in GPU memory) and host-to-host (input and output are in the memory of the host CPU). For the GPU-to-GPU case, we consider several refinements to a base GPU implementation and measure the performance gain from each refinement. For the host-to-host case, we analyze two strategies to communicate between the host and the GPU and show that one is optimal with respect to runtime while the other requires less device memory. This analysis is done for GPUs with one I/O channel to the host as well as those with 2. Experiments conducted on an NVIDIA Tesla GT200 GPU that has 240 cores running off of a Xeon 2.8 GHz quad-core host CPU show that, for the GPU-to-GPU case, our Aho-Corasick GPU adaptation achieves a speedup between 8.5 and 9.5 relative to a single-thread CPU implementation and between 2.4 and 3.2 relative to the best multithreaded implementation. For the host-to-host case, the GPU AC code achieves a speedup of 3.1 relative to a single-threaded CPU implementation. However, the GPU is unable to deliver any speedup relative to the best multithreaded code running on the quad-core host. In fact, the measured speedups for the latter case ranged between 0.74 and 0.83. Early versions of our multipattern Boyer-Moore adaptations ran 7 to 10 percent slower than corresponding versions of the AC adaptations and we did not refine the multipattern Boyer-Moore codes further.]]></description>
			<pubDate><![CDATA[June  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6165263]]></guid>
			<volume>62</volume>
			<issue>6</issue>
			<startPage>1156</startPage>
			<endPage>1169</endPage>
			<fileSize>1444</fileSize>
			<authors><![CDATA[Zha, Xinyan;Sahni, Sartaj;]]></authors>
		</item>
		<item>
			<title><![CDATA[Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6171158]]></link>
			<description><![CDATA[This paper presents an efficient decomposition scheme for hardware-efficient realization of discrete cosine transform (DCT) based on distributed arithmetic. We have proposed an efficient design for the implementation of cyclic convolution based on a group distributed arithmetic (GDA) technique where the read-only memory size could be reduced over the existing GDA-based design. The proposed structure for DCT implementation, based on the new decomposition scheme and proposed design of GDA-based cyclic convolution, involves significantly less area complexity than the existing one. For example, to implement the DCT of transform length $(N = 17)$, the proposed design needs a lookup table of 128 words, while the existing design for $(N = 16)$ requires a lookup table of 256 words. From the synthesis results, it is found that proposed design involves significantly less area, gives higher throughput, and consumes less power compared to the existing designs of nearly the same or lower lengths.]]></description>
			<pubDate><![CDATA[June  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6171158]]></guid>
			<volume>62</volume>
			<issue>6</issue>
			<startPage>1170</startPage>
			<endPage>1178</endPage>
			<fileSize>729</fileSize>
			<authors><![CDATA[Xie, Jiafeng;Meher, Pramod Kumar;He, Jianjun;]]></authors>
		</item>
		<item>
			<title><![CDATA[Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Softcore Processor]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6158641]]></link>
			<description><![CDATA[In this paper, we propose a new approach to implement a reliable softcore processor on SRAM-based FPGAs, which can mitigate radiation-induced temporary faults (single-event upsets (SEUs)) at moderate cost. A new Enhanced Lockstep scheme built using a pair of MicroBlaze cores is proposed and implemented on Xilinx Virtex-5 FPGA. Unlike the basic lockstep scheme, ours allows to detect and eliminate its internal temporary configuration upsets without interrupting normal functioning. Faults are detected and eliminated using a Configuration Engine built on the basis of the PicoBlaze core which, to avoid a single point of failure, is implemented as fault-tolerant using triple modular redundancy (TMR). A softcore processor can recover from configuration upsets through partial reconfiguration combined with roll-forward recovery. SEUs affecting logic which are significantly less likely than those affecting configuration are handled by checkpointing and rollback. Finally, to handle permanent faults, the tiling technique is also proposed. The new Enhanced Lockstep scheme requires significantly shorter error recovery time compared to conventional lockstep scheme and uses significantly smaller number of slices compared to known TMR-based design (although at the cost of longer error recovery time). The efficiency of the proposed approach was validated through fault injection experiments.]]></description>
			<pubDate><![CDATA[June  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6158641]]></guid>
			<volume>62</volume>
			<issue>6</issue>
			<startPage>1179</startPage>
			<endPage>1192</endPage>
			<fileSize>2363</fileSize>
			<authors><![CDATA[Pham, Hung-Manh;Pillement, S&#x00E9;bastien;Piestrak, Stanis&#x142;aw J.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Malwise&amp;#x2014;An Effective and Efficient Classification System for Packed and Polymorphic Malware]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6171162]]></link>
			<description><![CDATA[Signature-based malware detection systems have been a much used response to the pervasive problem of malware. Identification of malware variants is essential to a detection system and is made possible by identifying invariant characteristics in related samples. To classify the packed and polymorphic malware, this paper proposes a novel system, named Malwise, for malware classification using a fast application-level emulator to reverse the code packing transformation, and two flowgraph matching algorithms to perform classification. An exact flowgraph matching algorithm is employed that uses string-based signatures, and is able to detect malware with near real-time performance. Additionally, a more effective approximate flowgraph matching algorithm is proposed that uses the decompilation technique of structuring to generate string-based signatures amenable to the string edit distance. We use real and synthetic malware to demonstrate the effectiveness and efficiency of Malwise. Using more than 15,000 real malware, collected from honeypots, the effectiveness is validated by showing that there is an 88 percent probability that new malware is detected as a variant of existing malware. The efficiency is demonstrated from a smaller sample set of malware where 86 percent of the samples can be classified in under 1.3 seconds.]]></description>
			<pubDate><![CDATA[June  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6171162]]></guid>
			<volume>62</volume>
			<issue>6</issue>
			<startPage>1193</startPage>
			<endPage>1206</endPage>
			<fileSize>1473</fileSize>
			<authors><![CDATA[Cesare, Silvio;Xiang, Yang;Zhou, Wanlei;]]></authors>
		</item>
		<item>
			<title><![CDATA[On the Selection of Management/Monitoring Nodes in Highly Dynamic Networks]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6171161]]></link>
			<description><![CDATA[This paper addresses the problem of provisioning management/monitoring nodes within highly dynamic network environments, particularly virtual networks. In a network, where nodes and links may be spontaneously created and destroyed (perhaps rapidly) there is a need for stable and responsive management and monitoring, which does not create a large load (in terms of traffic or processing) for the system. A subset of nodes has to be chosen for management/monitoring, each of which will manage a subset of the nodes in the network. A new, simple, and locally optimal greedy algorithm called Pressure is provided for choice of node position to minimize traffic. This algorithm is combined with a system for predicting the lifespan of nodes, and a tunable parameter is also given so that a system operator could express a preference for elected nodes to be chosen to reduce traffic, to be &#x0022;stable,&amp;#x201D; or some compromise between these positions. The combined algorithm called PressureTime is lightweight and could be run in a distributed manner. The resulting algorithms are tested both in simulation and in a testbed environment of virtual routers. They perform well, both at reducing traffic and at choosing long lifespan nodes.]]></description>
			<pubDate><![CDATA[June  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6171161]]></guid>
			<volume>62</volume>
			<issue>6</issue>
			<startPage>1207</startPage>
			<endPage>1220</endPage>
			<fileSize>1187</fileSize>
			<authors><![CDATA[Clegg, Richard G.;Clayman, Stuart;Pavlou, George;Mamatas, Lefteris;Galis, Alex;]]></authors>
		</item>
		<item>
			<title><![CDATA[Sparse Learning-to-Rank via an Efficient Primal-Dual Algorithm]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6165264]]></link>
			<description><![CDATA[Learning-to-rank for information retrieval has gained increasing interest in recent years. Inspired by the success of sparse models, we consider the problem of sparse learning-to-rank, where the learned ranking models are constrained to be with only a few nonzero coefficients. We begin by formulating the sparse learning-to-rank problem as a convex optimization problem with a sparse-inducing $(ell_1)$ constraint. Since the $(ell_1)$ constraint is nondifferentiable, the critical issue arising here is how to efficiently solve the optimization problem. To address this issue, we propose a learning algorithm from the primal dual perspective. Furthermore, we prove that, after at most $(O({1over epsilon } ))$ iterations, the proposed algorithm can guarantee the obtainment of an $(epsilon)$-accurate solution. This convergence rate is better than that of the popular subgradient descent algorithm. i.e., $(O({1over epsilon^2} ))$. Empirical evaluation on several public benchmark data sets demonstrates the effectiveness of the proposed algorithm: 1) Compared to the methods that learn dense models, learning a ranking model with sparsity constraints significantly improves the ranking accuracies. 2) Compared to other methods for sparse learning-to-rank, the proposed algorithm tends to obtain sparser models and has superior performance gain on both ranking accuracies and training time. 3) Compared to several state-of-the-art algorithms, the ranking accuracies of the proposed algorithm are very competitive and stable.]]></description>
			<pubDate><![CDATA[June  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6165264]]></guid>
			<volume>62</volume>
			<issue>6</issue>
			<startPage>1221</startPage>
			<endPage>1233</endPage>
			<fileSize>1693</fileSize>
			<authors><![CDATA[Lai, Hanjiang;Pan, Yan;Liu, Cong;Lin, Liang;Wu, Jie;]]></authors>
		</item>
		<item>
			<title><![CDATA[Symbolic Model Checking for Incomplete Designs with Flexible Modeling of Unknowns]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6158639]]></link>
			<description><![CDATA[We consider the problem of checking whether an incomplete design (i.e., a design containing &#x0022;unknown parts&#x0022;, so-called Black Boxes) can still be extended to a complete design satisfying a given property or whether the property is satisfied for all possible extensions. There are many applications of property checking for incomplete designs, such as early verification checks for unfinished designs, error localization in faulty designs and the abstraction of complex parts of a design in order to simplify the property checking task. To process incomplete designs we present an approximate, yet sound algorithm. The algorithm is flexible in the sense that for every Black Box a different approximation method can be chosen. This permits us to handle less relevant Black Boxes (in terms of the property) with larger approximation and thus faster, whereas we do not lose important information when the possible effect of more relevant Black Boxes is modeled by more exact methods. Additionally, we present a concept to decide exactly whether Black Boxes with bounded memory can be implemented so that they satisfy a given property. This question is reduced to conventional symbolic model checking. The effectiveness and feasibility of the methods is demonstrated by a series of experimental results.]]></description>
			<pubDate><![CDATA[June  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6158639]]></guid>
			<volume>62</volume>
			<issue>6</issue>
			<startPage>1234</startPage>
			<endPage>1254</endPage>
			<fileSize>1201</fileSize>
			<authors><![CDATA[Nopper, Tobias;Scholl, Christoph;]]></authors>
		</item>
		<item>
			<title><![CDATA[Workload-Efficient Deadline and Period Assignment for Maintaining Temporal Consistency under EDF]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6171159]]></link>
			<description><![CDATA[Deriving deadlines and periods for update transactions so as to maintain timeliness and data freshness while minimizing imposed workload has long been recognized an important problem in real-time database research. Despite years of active research, the state-of-the-art still has much room for improvement, particularly for periodic transactions scheduled by the Earliest Deadline First (EDF) algorithm. In this paper, we propose a practical and efficient two-phase algorithm, GEneral EDF ($({cal G}{cal E}_{EDF})$), for assigning periods and deadlines to EDF-scheduled update transactions. Phase 1 of $({cal G}{cal E}_{EDF})$ aims at finding solutions for most inputs in linear time, based on the observation that the execution times of update transactions are relatively small compared to the validity interval lengths of real-time data objects in many real-time applications. In the remaining cases for which Phase 1 fails to derive solutions, Phase 2 is invoked by employing an existing deadline-monotonic-based algorithm, which we show is also applicable to our problem. Meanwhile, we have devised several techniques which significantly reduce the cost of schedulability test, and hence greatly improve time efficiency. Our experimental results demonstrate that $({cal G}{cal E}_{EDF})$ outperforms existing approaches in terms of generated workloads. Although Phase 2 has a pseudopolynomial time complexity, our experimental study shows that it runs much faster than other solutions with comparable quality.]]></description>
			<pubDate><![CDATA[June  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6171159]]></guid>
			<volume>62</volume>
			<issue>6</issue>
			<startPage>1255</startPage>
			<endPage>1268</endPage>
			<fileSize>1075</fileSize>
			<authors><![CDATA[Li, Jianjun;Xiong, Ming;Lee, Victor C.S.;Shu, LihChyun;Li, Guohui;]]></authors>
		</item>
		<item>
			<title><![CDATA[Complexity Analysis of Checkpoint Scheduling with Variable Costs]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6165262]]></link>
			<description><![CDATA[The parallel computing platforms available today are increasingly larger and thus, more and more subject to failures. Consequently it is necessary to develop efficient strategies providing safe and reliable completion for HPC parallel applications. Checkpointing is one of the most popular and efficient technique for developing fault-tolerant applications on such context. However, checkpoint operations are costly in terms of time, computation, and network communication. This will certainly affect the global performance of the application. In this work, we propose a performance model that expresses formally the checkpoint scheduling problem. This model exhibits the tradeoff between the impact of the checkpoints operations and the lost computation due to failures. Based on this model, we study the computational complexity of the problem of scheduling checkpoints with variable costs for general failure distributions. More precisely, we provide a new computational complexity analysis that explicits in depth the relations between the probabilistic failure model, the checkpoint cost, and the computational model. In particular, we prove that the checkpoint scheduling problem is NP-hard even in the simple case of uniform failure distribution. We also present a dynamic programming scheme for determining the optimal checkpointing times in all the variants of the problem.]]></description>
			<pubDate><![CDATA[June  2013]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6165262]]></guid>
			<volume>62</volume>
			<issue>6</issue>
			<startPage>1269</startPage>
			<endPage>1275</endPage>
			<fileSize>251</fileSize>
			<authors><![CDATA[Bouguerra, Mohamed-Slim;Trystram, Denis;Wagner, Fr&#x00E9;d&#x00E9;ric;]]></authors>
		</item>
	</channel>
</rss>