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TOC Alert for Publication# 12 2014December 18<![CDATA[Farewell State of the Journal Editorial]]>6411155<![CDATA[Editorial from the New Editor in Chief]]>6412237<![CDATA[In Memoriam [Ivan Stojmenovic]]]>6413330<![CDATA[A Novel En-Route Filtering Scheme Against False Data Injection Attacks in Cyber-Physical Networked Systems]]>6414182527<![CDATA[A Time Fairness-Based MAC Algorithm for Throughput Maximization in 802.11 Networks]]>64119312885<![CDATA[Accelerate RDP RAID-6 Scaling by Reducing Disk I/Os and XOR Operations]]>64132442594<![CDATA[Adaptive Voltage Scaling with In-Situ Detectors in Commercial FPGAs]]>64145531564<![CDATA[An Efficient and Trustworthy P2P and Social Network Integrated File Sharing System]]>64154702093<![CDATA[Channel-Hopping Scheme and Channel-Diverse Routing in Static Multi-Radio Multi-Hop Wireless Networks]]>64171863214<![CDATA[Completely Pinpointing the Missing RFID Tags in a Time-Efficient Way]]>64187961481<![CDATA[Coordinated Power and Performance Guarantee with Fuzzy MIMO Control in Virtualized Server Clusters]]>641971112368<![CDATA[Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)]]>$microhbox{m}$ -diameter, 6 $micro hbox{m}$-height through-silicon vias (TSVs) and $3.4nbspmicrohbox{m}$-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks.]]>6411121253173<![CDATA[Efficient Privacy-Preserving Ciphertext-Policy Attribute Based-Encryption and Broadcast Encryption]]> proposed a construction of CP-ABE with constant ciphertext. However, Herranz do not consider the recipients’ anonymity and the access policies are exposed to potential malicious attackers. On the other hand, existing privacy preserving schemes protect the anonymity but require bulky, linearly increasing ciphertext size. In this paper, we proposed a new construction of CP-ABE, named Privacy Preserving Constant CP-ABE (denoted as PP-CP-ABE) that significantly reduces the ciphertext to a constant size with any given number of attributes. Furthermore, PP-CP-ABE leverages a hidden policy construction such that the recipients’ privacy is preserved efficiently. As far as we know, PP-CP-ABE is the first construction with such properties. Furthermore, we developed a Privacy Preserving Attribute-Based Broadcast Encryption (PP-AB-BE) scheme. Compared to existing Broadcast Encryption (BE) schemes, PP-AB-BE is more flexible because a broadcasted message can be encrypted by an expressive hidden access policy, either with or without explicit specifying the receivers. Moreover, PP-AB-BE significantly reduces the storage and communication overhead to the order of ${mbi {O}}(log {mbi {N}})$, where ${mbi {N}}$ is the system size. Also, we proved, using information theoretical approaches, PP-AB-BE attains minimal bound on storage overhead for each user to cover all possible subgroups in the communication system.]]>6411261382223<![CDATA[Fool Me If You Can: Mimicking Attacks and Anti-Attacks in Cyberspace]]>6411391511290<![CDATA[Hardware–Software Coherence Protocol for the Coexistence of Caches and Local Memories]]>6411521651518<![CDATA[Requester-Based Spin Lock: A Scalable and Energy Efficient Locking Scheme on Multicore Systems]]>6411661791969<![CDATA[RRAM Defect Modeling and Failure Analysis Based on March Test and a Novel Squeeze-Search Scheme]]>2-based RRAM test chip. Results show that OF defects and R1D faults do exist in the RRAM chip. We also identify specific failure patterns from the test results, which are shown to be induced by multiple short defects between bit-lines. By identifying the defects and faults, designers and process engineers can improve the RRAM yield in a more cost-effective way.]]>6411111712<![CDATA[Scheduling Precedence Constrained Stochastic Tasks on Heterogeneous Cluster Systems]]>6411912042748<![CDATA[Scheme to Measure Packet Processing Time of a Remote Host through Estimation of End-Link Capacity]]>6412052183125<![CDATA[Selecting an Optimal Fault Tolerance Strategy for Reliable Service-Oriented Systems with Local and Global Constraints]]>6412192322480<![CDATA[Software Support and Evaluation of Hardware Transactional Memory on Blue Gene/Q]]>6412332462313<![CDATA[Testing Open Defects in Memristor-Based Memories]]>6412472592860<![CDATA[Time Series Characterization of Gaming Workload for Runtime Power Management]]>6412602731914<![CDATA[An Improved Approximation Ratio to the Partial-Terminal Steiner Tree Problem]]>${ G = (V,E)}$ with a metric cost function ${ c:E rightarrow {BBQ_ geq }}$ and two proper subsets $ R subset V$ and $ R^prime subseteq R$, a partial-terminal Steiner tree is a Steiner tree which contains all vertices in $it R$ such that all vertices in $R^prime$ must be leaves. The partial-terminal Steiner tree problem is to find a partial-terminal Steiner tree of the minimum cost in $G$. The previously best-known approximation ratio of the problem is $ 2rho$, where $bf rho$ is the approximation ratio of the Steiner tree problem. In this paper, we improve the ratio from $ 2rho$ to $ 2rho - {rho over {3rho - 2}} - f$, where $f$ is a non-negative function whose value is between 0 and $ rho - {rho over {3rho - 2}}$.]]>6412742791728<![CDATA[Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF)]]>641280285988<![CDATA[Stabilizing CPU Frequency and Voltage for Temperature-Aware DVFS in Mobile Devices]]>6412862921518<![CDATA[Comment on “High Speed Parallel Decimal Multiplication With Redundant Internal Encodings”]]> propose a new method for parallel decimal multiplication with redundant partial products. They compare the performance of their multiplier with some previous relevant works, based on analytical and synthesis results. We have noted that the claimed critical delay path in (IEEE Trans. Computers, vol. 62, no. 5, pp. 956–968, May 2013) is faster than the actual critical delay path. Therefore, comparison results seem to be deceptive. For example, our accurate analytical evaluation devaluated the claimed speed advantage over the multiplier of (Microelectronics J., vol. 40, no. 10, pp. 1471–1481, Oct. 2009). Furthermore, we synthesized both multipliers, to show synthesis results confirm those of analytical evaluation.]]>641293294421<![CDATA[2014 Reviewers List*]]>64129530268<![CDATA[2014 Index IEEE Transactions on Computers Vol. 63]]>641130578