<![CDATA[ IEEE Transactions on Computers - new TOC ]]>
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TOC Alert for Publication# 12 2016June 27<![CDATA[State of the Journal]]>65720142018306<![CDATA[A Systematic Methodology for Optimization of Applications Utilizing Concurrent Data Structures]]>657201920311764<![CDATA[Comparison between Binary and Decimal Floating-Point Numbers]]>65720322044299<![CDATA[Configurable XOR Hash Functions for Banked Scratchpad Memories in GPUs]]> bank indexing scheme. Although their bandwidth is fully exploited for linear memory accesses, their performance is burdened when non-unit strides appear in memory access patterns because they provoke bank conflicts. This paper explores the use of configurable bit-vector and bitwise XOR-based hash functions to evenly distribute memory addresses of the access patterns over the memory banks, reducing the number of bank conflicts. An exhaustive, but lightweight, search is used to configure bit-vector hash functions. Bitwise hash functions are configured with heuristics. Hardware and software implementations are carried out. For the hardware approach, the experimental results show 24 percent performance speed-up for 22 benchmarks on GPGPU-Sim, a Fermi-like simulator. Bank conflicts are reduced by 96 percent with bit-vector hash functions, and 97 percent with bitwise hash functions using our proposed Minimum Imbalance Heuristic. The software approach, using bit-vector hash functions, demonstrates 23 percent speed-up and 96 percent bank conflict reduction on a Fermi GPU, and 33 percent speed-up and 99 percent bank conflict reduction on a Kepler GPU.]]>657204520581108<![CDATA[Efficient Resource Constrained Scheduling Using Parallel Structure-Aware Pruning Techniques]]>657205920731016<![CDATA[Extended Generalized Feistel Networks Using Matrix Representation to Propose a New Lightweight Block Cipher: <sc>Lilliput</sc>]]>65720742089965<![CDATA[Fair Flow Control and Fairness Evaluation in Computer Networks and Systems]]>657209021031532<![CDATA[Global Optimization for Multi-Channel Wireless Data Broadcast with AH-Tree Indexing Scheme]]>, our algorithm can build a -ary AH-Tree index in . Next, we depict a new control table design, which eliminates up to 50 percent redundant entries while keeps the searching efficiency. We also theoretically prove that an optimal alphabetic tree has the minimum average tuning time among all tree-based index structures for skewed data broadcast. Thirdly, we design the new index and data allocation algorithms to further reduce the tuning time and access latency. The simulation results validate the effectiveness of our algorithms. In all, our global optimization mechanism can greatly improve the system performance and time efficiency for wireless data broadcast applications.]]>657210421171197<![CDATA[Link-Layer Multicast in Large-Scale 802.11n Wireless LANs with Smart Antennas]]>657211821331362<![CDATA[Modeling of Gaussian Network-Based Reconfigurable Network-on-Chip Designs]]>65721342142657<![CDATA[Multiple-Bit Parity-Based Concurrent Fault Detection Architecture for Parallel CRC Computation]]> percent for CRC with four parity bits, and corresponding time overhead is percent.]]>65721432157945<![CDATA[New Formats for Computing with Real-Numbers under Round-to-Nearest]]> number systems. This technique allows performing radix complement and round to nearest without carry propagation with negligible time and hardware cost. Furthermore, the proposed formats have the same storage cost and precision as standard ones. Since conversion to conventional formats simply require appending one extra-digit to the operands, standard circuits may be used to perform arithmetic operations with operands under the new format. We also extend the features of the RN-representation system and carry out a thorough comparison between both representation systems. We conclude that the proposed representation system is generally more adequate to implement systems for computation with real number under round-to-nearest.]]>65721582168517<![CDATA[NV-Tree: A Consistent and Workload-Adaptive Tree Structure for Non-Volatile Memory]]>Tree. Based on our quantitative analysis for consistent tree structures, we propose NV-Tree, a consistent, cache-optimized and workload-adaptive B Tree variant with significantly reduced consistency cost (up to 96 percent reduction in CPU cache line flush). To further optimize NV-Tree under various workloads, we propose a workload-adaptive scheme in which the sizes of individual nodes can be dynamically adjusted to improve the performance over time. We implement and evaluate NV-Tree and NV-Store, a key-value store based on NV-Tree, on an NVDIMM server. NV-Tree outperforms the state-of-art consistent tree structures by up to 12X under write-intensive workloads. NV-Store increases the throughput by up to 7.3X under YCSB workloads compared to Redis.]]>657216921831334<![CDATA[Performance Prediction for Large-Scale Parallel Applications Using Representative Replay]]>657218421982001<![CDATA[PSBS: Practical Size-Based Scheduling]]>657219922121340<![CDATA[Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation]]>657221322273031<![CDATA[Remote Transaction Commit: Centralizing Software Transactional Memory Commits]]>65722282240914<![CDATA[Resource Conscious Diagnosis and Reconfiguration for NoC Permanent Faults]]> fewer nodes and provides greater than 25 percent throughput improvement (beyond 15 faults) when compared to other state-of-the-art fault-tolerance solutions. uDIREC's improvement over prior-art grows further with more faults, making it a effective NoC reliability solution for a wide range of fault rates.]]>657224122562380<![CDATA[Scalable Multi-Match Packet Classification Using TCAM and SRAM]]>657225722691467<![CDATA[Symbol Shifting: Tolerating More Faults in PCM Blocks]]>657227022831117<![CDATA[Test Algorithms for ECC-Based Memory Repair in Ultimate CMOS and Post-CMOS]]>65722842298657<![CDATA[Truthful Mechanisms for Competitive Reward-Based Scheduling]]>65722992312471<![CDATA[Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems]]>657231323241322<![CDATA[Achieving Simple, Secure and Efficient Hierarchical Access Control in Cloud Computing]]>65723252331584<![CDATA[Improving the Accuracy of Defect Diagnosis with Multiple Sets of Candidate Faults]]>65723322338193<![CDATA[Testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs]]>65723392345780