<![CDATA[ Computer Architecture Letters - new TOC ]]> http://ieeexplore.ieee.org TOC Alert for Publication# 10208 2012 February 10 <![CDATA[Cover 1]]> 10 2 c1 c1 101 <![CDATA[Cover 2]]> 10 2 c2 c2 115 <![CDATA[Heterogeneity in “Homogeneous” Warehouse-Scale Computers: A Performance Opportunity]]> 10 2 29 32 145 <![CDATA[Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks]]> 10 2 33 36 139 <![CDATA[Exploring the Interaction Between Device Lifetime Reliability and Security Vulnerabilities]]> 10 2 37 40 142 <![CDATA[Fault-Tolerant Vertical Link Design for Effective 3D Stacking]]> 10 2 41 44 128 <![CDATA[Experience with Improving Distributed Shared Cache Performance on Tilera's Tile Processor]]> 10 2 45 48 377 <![CDATA[Multilevel Cache Modeling for Chip-Multiprocessor Systems]]> 10 2 49 52 440 <![CDATA[On Supporting Rapid Thermal Analysis]]> 10 2 53 56 377 <![CDATA[Cover 3]]> 10 2 c3 c3 115 <![CDATA[Cover 4]]> 10 2 c4 c4 101