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		<title><![CDATA[ Circuits and Devices Magazine, IEEE - new TOC ]]></title>
		<link>http://ieeexplore.ieee.org</link>
		<description>TOC Alert for Publication# 101 </description>
		<year>2008</year>
		<month>February </month>
		<day>06</day>
		<item>
			<title><![CDATA[IEEE Circuits and Devices Magazine]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099502.pdf?isnumber=4099335&arnumber=4099502]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099502]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>c1</startPage>
			<endPage>c1</endPage>
			<fileSize>1400</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Member Digital Library]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099503.pdf?isnumber=4099335&arnumber=4099503]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099503]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>c2</startPage>
			<endPage>c2</endPage>
			<fileSize>214</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Circuits and Devices - Table of contents]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099504.pdf?isnumber=4099335&arnumber=4099504]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099504]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>1</startPage>
			<endPage>1</endPage>
			<fileSize>86</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[From the Editor - Going...Going ...Gone!!!]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099505.pdf?isnumber=4099335&arnumber=4099505]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099505]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>2</startPage>
			<endPage>2</endPage>
			<fileSize>41</fileSize>
			<authors><![CDATA[Waynant, R.W.W.;]]></authors>
		</item>
		<item>
			<title><![CDATA[VLSI Designer's Interface]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099507.pdf?isnumber=4099335&arnumber=4099507]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099507]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>3</startPage>
			<endPage>5</endPage>
			<fileSize>99</fileSize>
			<authors><![CDATA[Bouldin, D.W.;]]></authors>
		</item>
		<item>
			<title><![CDATA[The CHIP - Peak Detectors for Multistandard Wireless Receivers]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099508.pdf?isnumber=4099335&arnumber=4099508]]></link>
			<description><![CDATA[Peak detectors (or envelope detectors) are commonly found in modern communication receivers mainly as a building block of automatic gain control (AGC) loops. The main function of the peak detectors is to detect the peak value of an input signal and track the peak over time. In this paper, some of peak detector topologies and their applications in multistandard wireless receivers was presented]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099508]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>6</startPage>
			<endPage>9</endPage>
			<fileSize>548</fileSize>
			<authors><![CDATA[Seok-Bae Park;Seok-Rae Park;Wilson, J.E.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Super Junction LDMOS Transistors - Implementing super junction LDMOS transistors to overcome substrate depletion effects]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099509.pdf?isnumber=4099335&arnumber=4099509]]></link>
			<description><![CDATA[The super junction (SJ) concept (Coe et al.) applied to power semiconductor devices is attractive due to its potential for reducing on-resistance at a given breakdown voltage. Discrete SJ vertical power devices have recently become available commercially. However, lateral SJ devices have not materialized for several years partly due to the fact that the lateral SJ structure, implemented on silicon substrates, suffers from substrate-assisted depletion effects which reduce the breakdown voltage. This article discusses the various device structures that have been proposed to eliminate the substrate-assisted depletion effects in SJ-lateral double diffused MOS LDMOS transistors (SJ-LDMOSTs). The concept of the SJ device and vertical and lateral SJ structure was summarized. The substrate-assisted depletion effects are described in detail. The alternative implementations proposed to suppress the substrate effects were then discussed. And the experimental implementation results are summarized and discussed to identify the most likely option for the implementation of lateral SJ-LDMOSTs]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099509]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>10</startPage>
			<endPage>15</endPage>
			<fileSize>832</fileSize>
			<authors><![CDATA[Il-Yong Park;Salama, C.A.T.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Tackling 4G challenges with "TACT" - Design and optimization of 4G radio receivers with a transceiver architecture comparison tool (TACT)]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099510.pdf?isnumber=4099335&arnumber=4099510]]></link>
			<description><![CDATA[Current integration trends imposed by the market are pushing toward the software radio paradigm. 4G radio receivers, where different wireless standards converge, make RF engineers face harder and harder challenges. Electronic design automation (EDA) tools play an increasing role in the design and verification of wireless system. This article presents a transceiver architecture comparison tool (TACT) which is a hierarchical, user-friendly, Matlab-based tool. It automates the design-space exploration procedure for 4G (fourth generation) wireless receivers. An example that considers a multistandard wideband code division multiple access (WCDMA)/wireless local area network (WLAN) receiver was also presented to illustrate the capabilities of TACT]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099510]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>16</startPage>
			<endPage>23</endPage>
			<fileSize>996</fileSize>
			<authors><![CDATA[Gonzalez, D.R.L.;Ana Rusu;Rusu, A.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Putting the "FLEX" in flexible mobile wireless radios - A wideband continuous-time baudpass sigma-delta ADC software radios]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099512.pdf?isnumber=4099335&arnumber=4099512]]></link>
			<description><![CDATA[This article has provided a brief overview of the SigmaDelta ADC conversion technologies for SDRs. The wireless receiver challenges were identified, the ADC design considerations and SigmaDelta solutions were discussed, and a low-distortion CT BP SigmaDelta modulator architecture was presented. The article has shown that the proposed CT BP SigmaDelta modulator is suitable for implementing high-IF ADC, making possible the software radio in handhelds. The major challenges in implementing such a high-IF ADC are the power dissipation and the degree of configurability, programmability, and adaptability that can be achieved by applying digital tuning and adaptive calibration]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099512]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>24</startPage>
			<endPage>30</endPage>
			<fileSize>929</fileSize>
			<authors><![CDATA[Ana Rusu;Rusu, A.;Ismail, M.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Predicting random jitter - Exploring the current simulation techniques for predicting the noise in oscillator, clock, and timing circuits]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099513.pdf?isnumber=4099335&arnumber=4099513]]></link>
			<description><![CDATA[The random jitter performance of clock, oscillator, and timing circuits can be predicted by using steady-state circuit simulation techniques that determine phase noise by analyzing the impact on phase due to thermal, flicker, channel, and shot noise present in the electronic devices. Given the phase noise response, and the steady-state operating conditions of the circuit, a wide variety of jitter measurements can be computed. Each involves a transformation of the phase noise results, with accuracy hinging on the quality of the phase noise response over a suitable range of offset frequencies]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099513]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>31</startPage>
			<endPage>38</endPage>
			<fileSize>720</fileSize>
			<authors><![CDATA[Wedge, S.;]]></authors>
		</item>
		<item>
			<title><![CDATA[RF subsystems implemented in mainstream CMOS - Overcoming special concerns affecting performance and cost]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099514.pdf?isnumber=4099335&arnumber=4099514]]></link>
			<description><![CDATA[Research is underway to explore the feasibility of implementing complete RF subsystems in standard mainstream CMOS processes without a need for any off-chip components. Progress to date has verified that RF circuits and on-chip antennas adequate for chip to chip communication can be realized, and it can be stated with some certainty that feasibility has been established. Radio architecture, signaling methodology, and individual circuit blocks have been devised and confirmed. It remains to demonstrate an on-chip reference with +/-150 ppm stability, optimize the individual circuit blocks, and demonstrate the overall concept in a single integrated chip]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099514]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>39</startPage>
			<endPage>46</endPage>
			<fileSize>1672</fileSize>
			<authors><![CDATA[Brewer, J.E.;Gao, L.;Sugavanam, A.;Lin, J.-J.;Su, Y.;Cao, C.;Ding, Y.-P.;Verma, A.;Yang, X.;Li, Z.;Wu, H.;Hwang, M.-H.;Hwang, S.-H.;Lin, J.;Bashrullah, R.;Fox, R.;Taubenheim, D.;Gorday, P.;Martin, F.;O, K.K.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Modeling and simulation of mixed-signal electronic designs - Enabling analog and discrete subsystems to be represented uniformly within a single framework]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099515.pdf?isnumber=4099335&arnumber=4099515]]></link>
			<description><![CDATA[This article has presented for the first time a scientific and mathematically sound principle that enables both analog and discrete subsystems to be represented uniformly within a single framework, thereby facilitating their simultaneous and uniform simulation within the same simulator. While the combination of the laboratory prototype analog subsystem simulator, DiamSim, and available discrete-event simulators such as VHDL constitute necessary and sufficient proof of the principle, the article outlines how a unified language and execution environment, nVHDL, may be realized for the future. In the coming age of networked computational systems (NCS), future complex systems will include analog hardware, synchronous and asynchronous discrete hardware, software, and inherently asynchronous networks that will interconnect both stationary and mobile entities, all governed by asynchronous control and coordination algorithms (Ghosh,2006). Paul (2006) believes that the current object-oriented programming is being quickly obsoleted by the increasing demands of net-centric warfare and that a dynamic, service-oriented architecture is critically needed to address key future needs of the US DoD. Logic dictates that nVHDL will likely play a key role in the development of a whole new approach, networked computational systems design language and execution environment (NCSDL). that will consist of a language in which complex systems may be described accurately and an execution environment that will permit the realistic execution of the executable description on a testbed to assess the system correctness, reliability, safety, security, and other performance parameters. Furthermore, to obtain results quickly for large systems and use them in iterating system designs, the testbed must consist of a network of workstations configured as a loosely-coupled parallel processor]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099515]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>47</startPage>
			<endPage>52</endPage>
			<fileSize>593</fileSize>
			<authors><![CDATA[Ghosh, S.;Giambiasi, N.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Embeded EEPROM Memory Achieving Lower Power - New design of EEPROM memory for RFID tag IC]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099517.pdf?isnumber=4099335&arnumber=4099517]]></link>
			<description><![CDATA[A 2-kb embedded EEPROM memory, operating over a wide voltage range (typically 2.5 V-5 V), was designed and fabricated using the SMIC 0.35-mum 2P3M CMOS embedded EEPROM process. The chip size is about 0.6 mm<sup>2</sup>. The method of adding control transistors improved the static power dissipation. The transient power consumption of the charge pump circuit was greatly reduced by using a slowly varying clock. The proposed SA using a voltage sensing method also significantly improved the read power dissipation. By employing these techniques, a low-power embedded EEPROM memory with 40 muA read current and 250 muA page write current was developed, that achieved much lower power than EEPROM memory designs reported in scientific journals or conferences. This EEPROM memory was used in the ISO/IEC 15693-compatible RFID tag IC project]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099517]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>53</startPage>
			<endPage>59</endPage>
			<fileSize>1195</fileSize>
			<authors><![CDATA[Liu Dong-Sheng;Zou Xue-Cheng;Zhang Fan;Deng Min;]]></authors>
		</item>
		<item>
			<title><![CDATA[Breaking the optical difraction barrier with nanophotonics - Ultrahigh-resolution bioimaging and biosensing in the subwavelength nanometric range with nanobiophotonic technologies]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099518.pdf?isnumber=4099335&arnumber=4099518]]></link>
			<description><![CDATA[The main goal of this study is to develop novel fiber-optic-based nanobiophotonics techniques for noninvasive imaging and biosensing optical properties of cellular and tissue samples beyond the diffraction barrier in the subwavelength nanoscale range. The work covers fundamental principles, recent developments, and trends in advanced nanobiophotonics techniques exploited for either minimally invasive diagnostics and imaging in biomedicine at cellular/intracellular level or development of nanosensors and nanostructured materials. Somerecently developed advanced ultrahigh-resolution nanotechnologies such as confocal nanoscopy and fiber-optic-based nanosensors, will also be discussed. These technologies allow one to break the theoretical optical diffraction barrier and to work in the subwavelength nanoscale range]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099518]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>60</startPage>
			<endPage>65</endPage>
			<fileSize>1052</fileSize>
			<authors><![CDATA[Ilev, I.K.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Ultraviolet laser beam and confocal microscopy - A system for rapid patterned photolysis]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099519.pdf?isnumber=4099335&arnumber=4099519]]></link>
			<description><![CDATA[Fluorescence microscopy is generally used for the research of biology, medical sciences and other life science fields. Especially, recent advances in laser technologies and in optical engineering have made it possible to investigate the nanoscale mechanisms of physiological and molecular biological processes and thus to extend its application to pathological and clinical investigations in therapeutic sciences. Furthermore, quantitative measurements of the small molecules, ions and proteins participated into the processes in living tissues, in vivo and in vitro, its movements, and locations can be observed with these optical technologies. Among them, the confocal microscopy was firstly invented for the purpose of visualization of such small-scale observations by using proper fluorescent molecules together with laser beams. Although contrast and resolution are degraded by strong scattering of the tissue preparations in the wide field conventional fluorescence microscope, the development of the confocal microscope can overcome some of the effects of scattering, since the detector pinhole rejects fluorescence from off-focus locations]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099519]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>66</startPage>
			<endPage>74</endPage>
			<fileSize>4935</fileSize>
			<authors><![CDATA[Kojima, H.;Simburger, E.;Boucsein, C.;Maruo, T.;Tsukada, M.;Okabe, S.;Aertsen, Ad.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Long travel ranges and accurate angular movement create new opportunities in biomedical manipulation systems]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099520.pdf?isnumber=4099335&arnumber=4099520]]></link>
			<description><![CDATA[A new class of unique linear and angular nanopositioners has been developed based on the novel properties of an advanced rotary piezoelectric motor. These new devices substantially improve positioning performance and open new possibilities for biomedical research studies]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099520]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>75</startPage>
			<endPage>78</endPage>
			<fileSize>1356</fileSize>
			<authors><![CDATA[Zhelyaskov, V.;Broderick, M.;Raphalovitz, A.;Davies, B.;]]></authors>
		</item>
		<item>
			<title><![CDATA[FEC in optical communications - A tutorial overview on the evolution of architectures and the future prospects of outband and inband FEC for optical communications]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099521.pdf?isnumber=4099335&arnumber=4099521]]></link>
			<description><![CDATA[The recent establishment of the 10/40 Gbps technology in DWDM optical links heralds a new era of bandwidth abundance, in response to an explosive growth of services provided through the Internet. Forward error correction (FEC) is one of the key-enabling elements in this long-awaited achievement. Borrowed from the wireless world, FEC was initially introduced in wavelength-division multiplex (WDM) optical-systems to combat amplified spontaneous emission (ASE), a form of noise native in optical amplifiers (OAs). These first generation FEC systems have been associated with a coding-gain of approximately 6 dB. However, as transmission rates gradually scaled towards 10 Gbps, other optical-impairments gained in significance, primarily nonlinear (NL) effects but also chromatic-dispersion (CD) and polarization mode dispersion (PMD). FEC turned out to be invaluable in mitigating these impairments as well]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099521]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>79</startPage>
			<endPage>86</endPage>
			<fileSize>3326</fileSize>
			<authors><![CDATA[Tychopoulos, A.;Koufopaulou, O.;Tomkos, I.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Book Reviews]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099523.pdf?isnumber=4099335&arnumber=4099523]]></link>
			<description><![CDATA[The following books are reviewed: Digital Logic and Microcomputer Design, 5th Ed. (Rafiquzzaman, M.; 2005); Engineering Thin Films and Nanostructures with Ion Beams (Knystautas, E., Ed.); Advanced Electronic Packaging, 2nd Ed. (Ulrich, R.N. and Brown, W.D.; 2006); Passive Micro-Optical Alignment Methods (Boudreau, R.A. and Boudreau, S.M., Eds.; 2005); Fundamentals of Wireless Communication (Tse, D. And Viswanath, P.; 2005); Theory of Remote Image Formation (Blahut, R.E.; 2005); Synthesis of Arithmetic Circuits (Deschamps, J. et al.; 2006); Semiconductor Material and Device Characterization (Schroder, D.K.; 2006); Design of Interconnection Networks for Programmable Logic (Lemieux, G. and Lewis, D.; 2003); Noise in High-Frequency Circuits and Oscillators (Schiek, B. et al.; 2006); Fiber to the Home: The New Empowerment (Green, P.E., Jr.; 2005); Fundamentals of Semiconductor Manufacturing and Process Control (May, G.S. and Spanos, C.J.; 2006); WCDMA Design Handbook (Richardson, A.; 2005); Phaselock Techniques, 3rd Ed. (Gardner, F.M.; 2005); Microwave Devices, Circuits and Subsystems (Glover, I.A. et al., Eds.; 2005); Modern Microwave and Millimeter-Wave Power Electronics (Barker, R.J. et al.; 2005); Fundamentals of Telecommunications, 2nd Ed. (Freeman, R.L.; 2005); Designing Digital Computer Systems with Verilog (Lilja, D.J. and Sapatnekar, S.S.; 2005).]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099523]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>87</startPage>
			<endPage>92</endPage>
			<fileSize>169</fileSize>
			<authors><![CDATA[Palumbo, G.;Rana, R.S.;Tessier, R.;Li, T.L.;Singh, G.P.;Mita, R.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Author Index]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099524.pdf?isnumber=4099335&arnumber=4099524]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099524]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>93</startPage>
			<endPage>102</endPage>
			<fileSize>414</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[IEEE Education Partners Program]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099525.pdf?isnumber=4099335&arnumber=4099525]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099525]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>103</startPage>
			<endPage>103</endPage>
			<fileSize>335</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
		<item>
			<title><![CDATA[Brain Teaser Chanllenge]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099527.pdf?isnumber=4099335&arnumber=4099527]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099527]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>105</startPage>
			<endPage>105</endPage>
			<fileSize>190</fileSize>
			<authors><![CDATA[Shadwell, B.;]]></authors>
		</item>
		<item>
			<title><![CDATA[Introducing ieee.tv]]></title>
			<link><![CDATA[http://ieeexplore.ieee.org/iel5/101/4099335/04099529.pdf?isnumber=4099335&arnumber=4099529]]></link>
			<description><![CDATA[ ]]></description>
			<pubDate><![CDATA[Nov.-Dec.  2006]]></pubDate>
			<guid><![CDATA[http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4099335&arnumber=4099529]]></guid>
			<volume>22</volume>
			<issue>6</issue>
			<startPage>106</startPage>
			<endPage>106</endPage>
			<fileSize>200</fileSize>
			<authors><![CDATA[]]></authors>
		</item>
	</channel>
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