<![CDATA[ IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Popular ]]>
http://ieeexplore.ieee.org
Popular Articles Alert for this Publication# 92 2017February <![CDATA[A Fully Integrated Discrete-Time Superheterodyne Receiver]]>2526356473106<![CDATA[Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator]]>2223433521188<![CDATA[Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit]]>2310200120081966<![CDATA[Streaming Elements for FPGA Signal and Image Processing Accelerators]]>246226222744008<![CDATA[VLSI Extreme Learning Machine: A Design Space Exploration]]>T in the range of 15-25 mV gives optimal results. An input weight matrix rotation method to extend the input dimension and hidden layer size beyond the physical limits imposed by the chip is also described. This allows us to overcome a major limit imposed on most hardware machine learners. The chip is implemented in a 0.35-μm CMOS process and occupies a die area of around 5 mm × 5 mm. Operating from a 1 V power supply, it achieves an energy efficiency of 0.47 pJ/MAC at a classification rate of 31.6 kHz.]]>25160743548<![CDATA[A 100-mA, 99.11% Current Efficiency, 2-mV<sub>pp</sub> Ripple Digitally Controlled LDO With Active Ripple Suppression]]>2 of the die area. The HD-LDO operates with an input voltage range of 1.43-2.0 V and an output voltage range of 1.0-1.57 V. At 100-mA load current, the HD-LDO achieves a current peak efficiency of 99.11% and a settling time of 15 clock periods with a 0.5-MHz clock for a current switching between 10 and 90 mA. The RCA suppresses fundamental, second, and third harmonics of the switching frequency by 13.7, 13.3, and 14.1 dB, respectively.]]>2526967042769<![CDATA[RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing]]>2523934011959<![CDATA[Low-Power and Area-Efficient Carry Select Adder]]>202371375291<![CDATA[Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon Era]]>2524274404404<![CDATA[Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application]]>252779782951<![CDATA[A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads]]>249297029824925<![CDATA[A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices]]>2513753791195<![CDATA[High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels]]>2424214334963<![CDATA[Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube]]>2).]]>2512102234781<![CDATA[Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication]]>25175862688<![CDATA[VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing]]>PP991122903<![CDATA[A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding]]>2527147243412<![CDATA[Efficient Designs of Multiported Memory on FPGA]]>2511391502187<![CDATA[A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations]]>2513543632711<![CDATA[Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator]]>2212262126281751<![CDATA[A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network]]>-12 for PRBS 31 and consumes 15.4 mW. The CDR occupies an active die area of 0.075 mm^{2}.]]>2513803841335<![CDATA[Built-in Self-Calibration and Digital-Trim Technique for 14-Bit SAR ADCs Achieving ±1 LSB INL]]>pp differential input signal. The proposed approach achieves 73.32-dB signal-to-noise and distortion ratio, which is an improvement of 12.03 dB after self-calibration at 400-kS/s sampling rate, consuming 90 mW from a ±15 V supply. The calibration circuitry occupies 28% of the capacitor DAC and consumes <;15 mW during operation. Measurement results show that this algorithm reduces integral nonlinearity from as high as 7 LSBs down to 1 LSB, and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces differential nonlinearity errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm_{2}.]]>2359169254930<![CDATA[Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application]]>2312278227901504<![CDATA[A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing]]>2538818932512<![CDATA[Low-Power FPGA Design Using Memoization-Based Approximate Computing]]>248266526783933<![CDATA[A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC]]>PP991142918<![CDATA[Digital Buck Converter With Switching Loss Reduction Scheme for Light Load Efficiency Enhancement]]>2527837871135<![CDATA[Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique]]>m). In the proposed design, a factoring technique is used to minimize switching power. To the best of our knowledge, factoring method has not been reported in the literature being used in the design of a finite field multiplier at an architectural level. Logic gate substitution is also utilized to reduce internal power. Our proposed design along with several existing similar works have been realized for GF(2^{233}) on ASIC platform, and a comparison is made between them. The synthesis results show that the proposed multiplier design consumes at least 27.8% lower total power than any previous work in comparison.]]>2524414492194<![CDATA[A Highly Efficient Ultralow Photovoltaic Power Harvesting System With MPPT for Internet of Things Smart Nodes]]>2, the proposed system can provide 0-29 μW of power, which is much higher than the commonly used passive radio-frequency identification devices in IOT application. The hill-climbing maximum power point tracking algorithm is developed in an energy-efficient manner to tune the input impedance of the system and guarantee adaptive maximum power transfer under wide illumination conditions. The detailed impedance tuning approach is implemented with a capacitor value modulation to eliminate the quiescent power consumption as well as to achieve a higher efficiency than the traditional pulse-frequency modulation scheme. A supercapacitor is utilized for buffering, energy storing, and filtering purposes, which enables more functions of the IOT smart nodes such as active sensing and system-on-chip (SOC) signal processing. The output voltage ranges between 3.0 and 3.5 V for different device loads, such as sensors, SOC, or wireless transceivers. The measured results confirm that this PV harvesting system achieves both ultralow operation capability under 20 μW and a selfsustaining efficiency of 89%.]]>2312306530755895<![CDATA[Design of Power and Area Efficient Approximate Multipliers]]>PP99152851<![CDATA[A Variation-Aware Adaptive Fuzzy Control System for Thermal Management of Microprocessors]]>2526836952876<![CDATA[Efficient Soft Cancelation Decoder Architectures for Polar Codes]]>15) decoding performance. When block size is large (e.g., N ≥ 2^{15}), the proposed RCSC algorithm reduces the required memory entries by more than 23% compared with the state-of-the-art FO-BP algorithm. The numerical results show that the error performance improvement of the RCSC algorithm is more significant when the SNR increases. For a different tradeoff, a reduced latency soft-cancelation (RLSC) algorithm is proposed to reduce the decoding latency and increase the throughput of the RCSC algorithm while slightly sacrificing decoding performance. Finally, the optimized VLSI architectures are presented for the RCSC and RLSC algorithms, respectively. The synthesis results demonstrate the efficiency of the proposed algorithms and architectures.]]>25187992473<![CDATA[A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications]]>2424444522647<![CDATA[A 170-dBΩ CMOS TIA With 52-pA Input-Referred Noise and 1-MHz Bandwidth for Very Low Current Sensing]]>PP991113509<![CDATA[An All-MOSFET Sub-1-V Voltage Reference With a —51 –dB PSR up to 60 MHz]]>2.]]>2539199282383<![CDATA[Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template]]>DD ranging from nominal voltage (1 V) to subthreshold voltage (~0.3 V). When six library cells embodying our proposed SAHB are compared with those embodying the conventional async QDI precharged half-buffer (PCHB) approach, the proposed SAHB cells collectively feature simultaneous -.64% lower power, -.21% faster, and ~6% smaller IC area; the PCHB cell is inappropriate for subthreshold operation. A prototype 64-bit Kogge-Stone pipeline adder based on the SAHB approach (at 65 nm CMOS) is designed. For a 1-GHz throughput and at nominal VDD, the design based on the SAHB approach simultaneously features -.56% lower energy and -.24% lower transistor count advantages than its PCHB counterpart. When benchmarked against the ubiquitous synchronous logic counterpart, our SAHB dissipates -.39% lower energy at the 1-GHz throughput.]]>2524024152766<![CDATA[A Single-Stage Low-Dropout Regulator With a Wide Dynamic Range for Generic Applications]]>o≤3.3 nF (capacitor-less) and C_{o}≥1 μF (with-capacitor).]]>246211721274183<![CDATA[Write Order-Based Garbage Collection Scheme for an LBA Scrambler Integrated SSD]]>2525105193324<![CDATA[A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications]]>DDL = 0.4 V, and high supply voltage level of V_{DDH} = 1.8 V.]]>253115411581221<![CDATA[Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication]]>2424344432263<![CDATA[High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder]]>253109811113544<![CDATA[Low-Power and Compact Analog-to-Digital Converter Using Spintronic Racetrack Memory Devices]]>2. The racetrack ADC is suitable for applications requiring dense ADC arrays, such as image sensors. This paper describes one ultrahigh speed digital pixel sensor imaging system benefiting from the racetrack ADC.]]>2539079182789<![CDATA[A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy]]>2512242374481<![CDATA[High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA]]>2511651763195<![CDATA[Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell]]>ON/I_{OFF} ratio of read path, and leakage power of the cell; Monte Carlo simulation results confirm the robustness of the proposed cell toward these issues. Layout drawn in a 45-nm technology rule shows that the proposed cell occupies 2.02× greater area as compared with 6T SRAM cells. However, 6.9× higher I_{ON}/I_{OFF} ratio of the read path of the proposed cell as compared with 6T cell holds potential to significantly subside the area overhead. A new figure of merit that comprehensively captures stability, delay, power dissipation, and area of an SRAM cell is also proposed. Based on the proposed metric, we observe that the proposed cell outperforms all, but one of the SRAM cells considered in this paper.]]>248263426429293<![CDATA[Design and Applications of Approximate Circuits by Gate-Level Pruning]]>PP99192728<![CDATA[A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS]]>253104410534217<![CDATA[Preweighted Linearized VCO Analog-to-Digital Converter]]>PP99151822<![CDATA[Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits]]>1055665812297<![CDATA[A CMOS PWM Transceiver Using Self-Referenced Edge Detection]]>-12) with small area occupation (540 μm^{2}). For reliability improvement, error check and correction associated with intercycle edge detection is introduced and its effectiveness is verified by 1-bit PWM measurement.]]>236114511491990