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Popular Articles Alert for this Publication# 8919 2017February <![CDATA[Processes of AM-PM Distortion in Large-Signal Single-FET Amplifiers]]>6422452603029<![CDATA[A Study of Operating Condition and Design Methods to Achieve the Upper Limit of Power Gain in Amplifiers at Near- $f_{max}$ Frequencies]]>max. Using the gain-plane approach, the necessary and sufficient conditions to achieve this theoretical upper limit are obtained and the results are analytically verified. As will be demonstrated, the maximum power gain is achieved if and only if the imaginary part of Y_{12}/Y_{21} becomes zero and the device operates at the edge of the unconditional stability region. In addition, a generic circuit solution comprising both a Y- and a Z-embedding network is proposed to achieve this upper limit. Simulations of a CMOS amplifier surrounded by an exemplary YZ-embedding network verify this study.]]>6422612712083<![CDATA[A General Theory of Phase Noise in Transconductor-Based Harmonic Oscillators]]>2 phase noise equations when the resonator consists of an arbitrary number of cascaded LC tanks, each tuned at a different harmonic of the oscillation frequency. We also show that the phase noise caused by transconductor white noise is always proportional to the phase noise caused by resonator losses, and that no flicker noise from the transconductor is up-converted into phase noise in an oscillator with an odd-symmetric voltage waveform. The phase noise for a number of different oscillators/resonators has been simulated, always obtaining an exceedingly good agreement between theoretical predictions and numerical results.]]>6424324451286<![CDATA[Time-Domain Analysis of Passive Mixer Impedance: A Switched-Capacitor Approach]]>6423473592894<![CDATA[A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers]]>6423103213650<![CDATA[Generalized High Step-Up DC-DC Boost-Based Converter With Gain Cell]]>6424804933473<![CDATA[Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC]]>6423223322316<![CDATA[The flipped voltage follower: a useful cell for low-voltage low-power circuit design]]>527127612911168<![CDATA[Analysis and Design of Power Harvesting Circuits for Ultra-Low Power Applications]]>6424714792759<![CDATA[Optimized Memristor-Based Multipliers]]>2 + 29N steps and 17N+3 memristors to 2N^{2} + 21N steps and 7N+1 memristors. A second implementation is proposed that is constructed from MAD gates, a lower-area, lower-delay alternative to IMPLY logic. This design performs an N-bit multiplication in N^{2} + N steps with 5N memristors and 3N+2 drivers. Both designs require fewer steps and less than 1/6 of the number of components of a traditional CMOS design. Finally, both of the implementations are extended to implement radix-2 Booth multipliers. The IMPLY design only increases by 1 step per iteration and 2N memristors and drivers. The MAD design increases by N memristors and 6N switches but maintains the same delay as the shift-and-add multiplier. Both designs maintain a lower area and lower delay than the CMOS equivalent.]]>6423733852548<![CDATA[A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC]]>6422832956620<![CDATA[Full On-Chip CMOS Low-Dropout Voltage Regulator]]>549187918901617<![CDATA[Wireless Power Transfer With Three-Ports Networks: Optimal Analytical Solutions]]>6424945031512<![CDATA[Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures]]>556144114541188<![CDATA[A 220-mV Power-on-Reset Based Self-Starter With 2-nW Quiescent Power for Thermoelectric Energy Harvesting Systems]]>6412172263502<![CDATA[A Two-Step Prediction ADC Architecture for Integrated Low Power Image Sensors]]>64150602841<![CDATA[Partial Dynamic Element Matching Technique for Digital-to-Analog Converters Used for Digital Harmonic-Cancelling Sine-Wave Synthesis]]>6422963094213<![CDATA[Reconfigurable Inductorless Wideband CMOS LNA for Wireless Communications]]>3 of +14.3 dBm, with 7 mW of power consumption. In low-power mode, it draws 1.5 mW, while providing a NF of 2.6 dB, a gain of 21 dB, and an I I P_{3} of 4.7 dBm. The active die area is 0.0072 mm^{2}.]]>6436756852398<![CDATA[A 5-GS/s 10-b 76-mW Time-Interleaved SAR ADC in 28 nm CMOS]]>PP991112423<![CDATA[Optimization Techniques for the Efficient Implementation of High-Rate Layered QC-LDPC Decoders]]>6424574702991<![CDATA[Post-Quantum Cryptography on FPGA Based on Isogenies on Elliptic Curves]]>p2, and minimizing pipeline stalls with optimal scheduling. Consequently, our results are also faster than software libraries running affine SIDH even on Intel Haswell processors. For our implementation at 85-bit quantum security and 128-bit classical security, we generate ephemeral public keys in 1.655 million cycles for Alice and 1.490 million cycles for Bob. We generate the shared secret in an additional 1.510 million cycles for Alice and 1.312 million cycles for Bob. On a Virtex-7, these results are approximately 1.5 times faster than known software implementations running the same 512-bit SIDH. Our results and observations show that the isogeny-based schemes can be implemented with high efficiency on reconfigurable hardware.]]>64186992769<![CDATA[Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial]]>58122361569<![CDATA[Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC–DC PWM Converters]]>5526876961294<![CDATA[A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency]]>587159116031735<![CDATA[The Circuit Theory Behind Coupled-Mode Magnetic Resonance-Based Wireless Power Transmission]]>Q) and large coupling distance. It simplifies the analysis by reducing the order of the differential equations by half compared to the circuit theory.]]>599206520742999<![CDATA[Introducing Suspendance Analysis]]>6423333463904<![CDATA[An All-Digital, Single-Bit RF Transmitter for Massive MIMO]]>6436967042228<![CDATA[A MPPT Circuit With 25 $mutext{W}$ Power Consumption and 99.7% Tracking Efficiency for PV Systems]]>2 and consumes less than 25 μW with the digital core running at 500 kHz and a measured peak MPP tracking efficiency of 99.7%.]]>6422722823377<![CDATA[Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction]]>6424094182064<![CDATA[Frequency-Channelized Mismatch-Shaped Quadrature Data Converters for Carrier Aggregation in MU-MIMO LTE-A]]>6413132915<![CDATA[Device Modelling for Bendable Piezoelectric FET-Based Touch Sensing System]]>6312220022081903<![CDATA[A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection]]>2, including 140 pF of stacked on-chip capacitors.]]>6237077162674<![CDATA[A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching]]>2. At 0.35-to-0.5 V supply voltage and 0.3-to-2 MS/s sampling rate with a Nyquist input, the ADC achieves a signal-to-noise-plus-distortion ratio (SNDR) of 55.5 dB to 56.3 dB and a corresponding effective number of bits (ENOB) of 8.92 bit to 9.06 bit respectively with a power consumption of 0.3 μW to 2.5 μW and a resulting figure of merit (FoM) from 1.94 fJ/conversion-step to 2.32 fJ/conversion-step.]]>6312214921573135<![CDATA[Implications of Passive Mixer Transparency for Impedance Matching and Noise Figure in Passive Mixer-First Receivers]]>571230923103559<![CDATA[A 73.9%-Efficiency CMOS Rectifier Using a Lower DC Feeding (LDCF) Self-Body-Biasing Technique for Far-Field RF Energy-Harvesting Systems]]>th) which improves the power conversion efficiency (PCE) when the rectifier is operating at a smaller received power. A 9.5% of improvement is achieved at the peak PCE when the rectifier is operating at 953 MHz, and driving a 10 kQ load. A maximum PCE of 73.9% is measured at 2 GHz when driving a 2-kQ load. The LDCF technique also offers a self-limiting capability for its output voltage, by reducing the PCE at larger received power. A limit-voltage level of 3.5 V is measured irrespective to the operating frequency and load. This capability aids the protection of the subsequent circuits in a wireless sensor from being overpowered.]]>64499210023861<![CDATA[A frequency compensation scheme for LDO voltage regulators]]>51610411050576<![CDATA[Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial]]>5913291561<![CDATA[Design and Analysis of CMOS LNAs with Transformer Feedback for Wideband Input Matching and Noise Cancellation]]>PP991102350<![CDATA[A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90-nm CMOS]]>2. The prototype consumes 67.3 nW at 150 kS/s from a single 0.3 V supply voltage and achieves an ENOB of 8.85 bits and an SFDR of 70.7 dB at Nyquist input, respectively. The resultant Walden's FoM and Schreier's FoM are 0.97 fJ/conv.-step and 175.5 dB, respectively.]]>6435625724522<![CDATA[An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and Modulator for IoT Applications in 40 nm CMOS]]>PP991124181<![CDATA[Universal Current-Mode Control Schemes to Charge Li-Ion Batteries Under DC/PV Source]]>639153115424241<![CDATA[A Self-Powered and Optimal SSHI Circuit Integrated With an Active Rectifier for Piezoelectric Energy Harvesting]]>2. Measured results indicate that the proposed circuit increases the amount of power harvested from a piezoelectric cantilever by 2.1 times when compared with a full bridge (FB) rectifier and achieves a power conversion efficiency of 85%. The proposed circuit dissipates about 24 μW while the controller alone only 1.5 μW.]]>6435375492585<![CDATA[Analysis and Optimization of Direct-Conversion Receivers With 25% Duty-Cycle Current-Driven Passive Mixers]]>579235323662929<![CDATA[Series-Parallel Charge Pump Conditioning Circuits for Electrostatic Kinetic Energy Harvesting]]>6412272401317<![CDATA[Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division]]>90 nm technology ASIC implementation. Two versions of proposed architecture are presented, one with single stage multiplier and another with two stage multiplier. Compared to a standalone double precision division architecture, the proposed dual-mode architecture requires 17% to 19% extra hardware resources, with 3% to 5% period overhead. In comparison to prior art on this, the proposed architecture out-performs them in terms of required area, time-period and throughput.]]>6423863982143<![CDATA[Consensus of Multiagent Systems and Synchronization of Complex Networks: A Unified Viewpoint]]>5712132241045<![CDATA[A 2.24-mW, 61.8-dB SNDR, 20-MS/s Pipelined ADC With Charge-Pump-Based Dynamic Biasing for Power Reduction in Op Amp Sharing]]>PP991122684<![CDATA[Digital Blind Background Calibration of Imperfections in Time-Interleaved ADCs]]>PP991112655<![CDATA[A Wide-Range Level Shifter Using a Modified Wilson Current Mirror Hybrid Buffer]]>616165616652416<![CDATA[A 4-Element 60-GHz CMOS Phased-Array Receiver With Beamforming Calibration]]>2 excluding pads.]]>6436426522894