Abstract
Beginning with a brief review of CMOS scaling trends from 1 µm to 0.1 µm, this tutorial examines the fundamental factors that will ultimately limit CMOS scaling and considers the design issues near the limit of scaling. The fundamental limiting factors are electron thermal energy, tunneling leakage through gate oxide, and 2D electrostatic scale length. Both the standby power and the active power of a processor chip will increase precipitously below the 0.1-µm or 100-nm technology generation. To extend CMOS scaling to the shortest channel length possible while still gaining significant performance benefit, an optimized, vertically and laterally nonuniform doping design (superhalo) is presented. It is projected that room-temperature CMOS will be scaled to 20-nm channel length with the superhalo profile. Low-temperature CMOS allows additional design space to further extend CMOS scaling to near 10 nm.

Educational Course Subject Areas
Circuits & Devices

Keywords
CMOS ,  kT ,  QM ,  High k ,  tunneling ,  subthreshold ,  halo ,  scale length ,  volume inversion ,  FinFET