Deposited SiO/sub 2/ as the insulator for GaInAs and InP MISFETs

It is shown that low-temperature-deposited SiO/sub 2/ is a good insulator for InP and GaInAs MISFETs. Long-term (16-h) 300 degrees C H/sub 2/ anneals reduce interface state density, oxide fixed charge, and C-V hysteresis. D/sub it/ values of 10/sup 10/-10/sup 11/ cm/sup 2/ eV/sup -1/ (suitable for MISFET operation) are routinely obtained. It is concluded that the hysteresis results from charge trapping at the semiconductor-insulator interface, possibly in a thin native oxide layer formed during the SiO/sub 2/ deposition, and/or from P (As) vacancies in the InP (GaInAs) surface resulting from preferential oxidation of the InP. Ion-implanted, self-aligned-gate MISFETs showed drain current drifts of approximately 5% over 10/sup 3/ s at room temperature for InP, and <2% over a 74-h period at 50 degrees C for GaInAs. The use of surface modification techniques such as P overpressure and surface sulfidation holds promise for eliminating this problem. These results and the performance of MISFETs in microwave and gigabit-rate logic demonstrate that low-temperature-deposited SiO/sub 2/ is an excellent gate insulator for InP and GaInAs MISFETs, and that these materials have great potential for high performance microwave, millimeter-wave, and gigabit-rate logic circuit applications.<
>