Closing the loop between analog design and test

By the time volume production test statistics are known, it is usually too late for designers to modify an analog design to improve test cost or coverage, or to add redundancy to improve yield or reliability. Analog fault simulation could provide immediate feedback to designers about the impact of design on production test time, test cost, and test coverage of manufacturing defects, but simulating all such defects is usually not feasible. This paper describes an analog defect simulator developed for industrial mixed-signal circuits. It simulates realistic random defects, and reports likelihood-weighted defect coverage based on user-provided likelihoods for opens, shorts, and excessive variations, and for user-defined defects. An additional benefit of defect simulation is measurement of a circuit's defect tolerance, whether the tolerance is added to improve reliability or yield.