Performance of parallel prefix circuit transition localization of pulsed waveforms

An early step in measuring jitter in communication signals is locating the transitions, the points in time when the waveform changes between logic levels. Transition localization can be the most time-consuming step in jitter measurement because it is the last step where every sample must be processed. We transform the localization FSM (finite state machine) into a Cayley table of a semigroup equivalent to the FSM, in the sense that FSM execution is equivalent to taking products over the semigroup, enabling highly parallel localization yeilding high, gapless throughput. We describe a novel, parallel hardware architecture for executing these semigroup products. We evaluate the practical potential of this approach using two exemplar FSM's, studying the throughput and hardware resource consumption of FPGA (field-programmable gate array) of this parallel architecture, varying two parameters: one that controls FSM size and another that controls the peak hardware parallelism. We use a state of the art FPGA as the technology model, reporting resulting sample rate, power, and resource consumption for a range of designs. These results show that for the simplest FSMs, samples can be examined for transitions at rates as high as 40 gigasamples/second (GSa/s) can be achieved, but that sample rate decreases rapidly for increased p. Also, the explosion in resource requirements with increase p limits data parallelism to below 1024 samples. Likewise, power consumption can be a significant limit for large FSMs.