100–166 GHz wide band high speed digital dynamic frequency divider design in 0.13 μm SiGe BiCMOS technology

Design of a digital dynamic divider in SiGe bipolar technology is presented in this paper. The proposed digital dynamic frequency divider is based on two latches connected with negative feedback. However, in contrast to the conventional static frequency divider the latching differential pair has been completely omitted to reduce the load for the sensing differential pair to extend the maximum operating frequency. Two versions of dynamic dividers (A and B) are fabricated to validate the concept. The divide ratio for version A is two while that for version B is four. In version B, the divide ratio of four is achieved by cascading a conventional static frequency divider by two in front of version A. The circuits are fabricated in IHP 0.13 μm SiGe BiCMOS technology with ft and f
_max
of 300 GHz and 500 GHz, respectively. The input referred self-oscillation frequency (SOF) of 149 GHz was measured. With single-ended sine wave clock input, both dividers are operational from 100 to 166 GHz. At dual power supply with V
_cc
= 3 V and V
_ee
= -1.9 V, the version A and B consume 80 mA and 160 mA (without output buffers), respectively.