Parallel Random Access Memory in a shared memory architecture

Parallel algorithms can significantly speed up computing performance. However, parallel architecture often needs shared-memories for concurrent access. Conventionally, parallel memories are constructed as space-multiplexed memories with many memory chips connected in parallel. This architecture normally requires a large number of interconnects with potentially large routing delay and consumes massive area. This proposal develops a new memory component called Parallel Random Access Memory (P-RAM) with four identical parallel ports. This component is designed using VHDL hardware description language and emulated on Cyclone II FPGA. The P-RAM is not a conventional RAM memory since its four ports can be read and write concurrently. It can be used for many purposes such as shared memory for multiple processors in a parallel model.