Digital logic synthesis using genetic algorithms

This work explores the feasibility of using genetic algorithms (GAs) as a synthesizing tool for transistor-level MOS logic design. The p and nMOS transistors are modeled as neurons that are massively connected, and are configured as a network for input and output logic mapping. Each transistor has two inputs G and S that correspond to, respectively, the gate and source of a transistor while output is directed from the drain D. Digital circuit design is then transformed into an optimization problem that can make use of the optimization techniques developed in the framework of GAs. Transistors share a sigmoidal output characteristics, and a fitness function is conceived so that GA can be applied for circuit optimization. The pruning capability of both connections and devices is embedded in the cost function so as to achieve an optimal design. Operations of the designed circuit are verified by using PSPICE.