FPGA implementations of real-time detectors for a spectrally efficient FDM system

A new method for detecting Spectrally Efficient Frequency Division Multiplexing (SEFDM) is proposed and verified through modelling and practical FPGA implementation. The method is derived through studies of two sphere decoding techniques, namely Fixed SD (FSD) with Sort-Free (SF) and Non-Sort-Free (NSF) algorithms. We report a co-simulation verification framework to verify the performance of these detectors and to choose an optimum design. Finally, a hybrid detector Truncated Singular Value Decomposition-Fixed Sphere Detector (TSVD-FSD) is tested on the FPGA platform. Error behaviour is studied for the practical FPGA system and then compared with theoretical/ideal modelling. Detailed analysis indicates the suitability of our design and implementation methods for SEFDM detection with 16 carriers and 25% bandwidth saving.