A configurable high-throughput linear sorter system

Popular sorting algorithms do not translate well into hardware implementations. Instead, hardware-based solutions like sorting networks and linear sorters exploit parallelism to increase sorting efficiency. Linear sorters, built from identical nodes with simple control, have less area and latency than sorting networks, but they are limited in their throughput. We present a system composed of multiple linear sorters acting in parallel in order to increase throughput. Interleaving is used to increase bandwidth and allow sorting of multiple values per clock cycle, and the amount of interleaving and depth of the linear sorters can be adapted to suit specific applications. Implementation of this system into a Field Programmable Gate Array (FPGA) results in a speedup of 68 compared to quicksort running in a MicroBlaze processor.

I. Introduction

Sorting is an essential function for many scientific and data processing applications. Extensive research has optimized multiple software sorting algorithms for general-purpose computing, thereby assisting applications to achieve higher performance. The need for higher performance has also motivated the migration of sorting algorithms into specialized hardware. However many of the assumptions made to increase performance on a general-purpose processor do not hold for custom hardware implementations. When directly translated to a hardware processor, the software algorithms can quickly degrade into a series of data retrievals, comparisons, swaps and writes; all problems that can be magnified in systems with low processor speeds, limited storage, disabled caches and high latency memory access times.