A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling

This paper presents a 4.3 GB/s mobile memory interface that utilizes low power states with rapid transition times to support power efficient signaling over a wide range of effective bandwidths. The fastest power state transition is implemented by a global synchronous clock pause that gates dynamic power consumption without any loss of system state. Extensive use of CMOS circuit topologies, with low static power consumption, provides maximum power savings when the clocks are paused. The memory controller forwards a half bit-rate clock to the memory for synchronous communication, which is similarly paused in the low power state. Thus, dynamic interface power on the memory itself naturally responds to the clock pausing, without any explicit communication from the controller or special low-power state on the memory. Low-swing differential signaling based on a push-pull voltage mode driver results in good signal integrity and power efficiency at peak activity. Test-chips fabricated in a 40 nm low-power CMOS technology achieve 3.3 mW/Gb/s power efficiency at 4.3 GB/s data bandwidth, and support better than 5 mW/Gb/s operation over a range from 0.03 to 4.3 GB/s.