A 31 ns Random Cycle VCAT-Based 4F $^{2}$ DRAM With Manufacturability and Enhanced Cell Efficiency

A functional 4F
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DRAM was implemented based on the technology combination of stack capacitor and surrounding-gate vertical channel access transistor (VCAT). A high performance VCAT has been developed showing excellent Ion-Ioff characteristics with more than twice turn-on current compared with the conventional recessed channel access transistor (RCAT). A new design methodology has been applied to accommodate 4F
²
cell array, achieving both high performance and manufacturability. Especially, core block restructuring, word line (WL) strapping and hybrid bit line (BL) sense-amplifier (SA) scheme play an important role for enhancing AC performance and cell efficiency. A 50 Mb test chip was fabricated by 80 nm design rule and the measured random cycle time (tRC) and read latency (tRCD) are 31 ns and 8 ns, respectively. The median retention time for 88 Kb sample array is about 30 s at 90°C under dynamic operations. The core array size is reduced by 29% compared with conventional 6F
²
DRAM.