Disturb-Free Writing Operation for Ferroelectric-Gate Field-Effect Transistor Memories With Intermediate Electrodes

To achieve disturb-free writing, we proposed a new writing operation for ferroelectric-gate field-effect transistor memories with intermediate electrodes. The writing voltages V
_W
applied to the wordlines for Pr
⁺
and Pr
⁰
memory states are the same pulse magnitudes, which consist of V
_W

⁺
followed by V
_W

^-
, whereas the bias timings of the bitline voltages differ from each other. The bitline voltage for the Pr
⁺
memory state is set high when V
_W
is set V
_W

⁺
, and it is set to low by the time when V
_W
is changed to V
_W

^-
. On the other hand, the bitline voltage for the Pr
⁰
memory state is set high until the whole writing pulse of (V
_W

⁺
+ V
_W

^-
) is finished. This is verified experimentally using a discrete circuit, which showed that the new writing operation achieves disturb-free writing. The memory consists of two transistors for data writing and reading. With the obtained experimental results, we discuss the possibilities of high integration of this memory as well as low reading voltage.