A data-path multiplier with automatic insertion of pipeline stages

The architecture of an easy-to-use, highly configurable, compiled pipelined multiplier is described. The multiplier is designed for use in high-performance pipelined data paths such as those found in digital signal processing applications. The multiplier compiler allows the data-path designer to control the bit width of the multiplier as well as the clock-cycle time, setup time, and output-delay time. Given these parameters, the multiplier compiler uses a simple timing model to decide where pipeline stages should be inserted into the multiplier and generates a pipelined multiplier that meets the designer's system requirements.