Correlating Microscopic and Macroscopic Variation With Surface-Potential Compact Model

Variation analysis of n-MOSFETs fabricated by different manufacturers at three technology nodes (180, 100, and 65 nm) demonstrates that surface-potential compact models are capable to bridge the gap between circuit simulation and TCAD by enabling extraction of microscopic MOSFET-parameter variation from measured macroscopic V
_th
and I
_on
variations. Considering only the four microscopic variations of substrate doping, pocket-implantation doping, carrier mobility degradation due to gate-interface roughness, and channel-length change, is found sufficient to reproduce within-wafer V
_th
and I
_on
variations of wide MOSFETs (W
_g
= 10 mum) for all L
_g
and all three technology nodes. Extracted microscopic variation reductions between 180- and 65-nm nodes range from 25% for pocket doping to 70% for carrier mobility degradation. However, V
_th
and I
_on
variations at shortest L
_g
remain approximately constant for all three technologies, in spite of the substantial variation reductions at the microscopic level.