Implementation issues for on-chip learning with analogue VLSI MLPS

Microelectronic neural network technology has become sufficiently mature over the past few years that reliable performance can now be obtained from VLSI circuits under carefully controlled conditions. The use of analogue VLSI allows low power, low cost and area efficient hardware realisations which can perform the computationally intensive feed-forward operation of neural networks at high speed. These factors, coupled with the ability to interface directly with the analogue world, make real-time applications a possibility. This paper attempts to address some of the issues concerning in-situ learning with analogue VLSI multilayer perceptron (MLP) networks. We consider the modes used to train analogue neural networks, study weight storage and circuit precision issues, and identify the most promising training algorithms. We then make some conclusions based on results from analogue VLSI chips that we have designed, built and successfully tested.