Design of a 6 bit 1.25 GS/s DAC for WPAN

This paper describes a 6 bit 1.25GS/s DAC for WPAN transceivers. The proposed DAC is designed with a current steering segmented 2+4 architecture to achieve low power consumption and a small die area. A master-slave deglitch circuit and regulated cascode current sources are proposed to improve the dynamic performance of the DAC. The DAC, implemented in a 0.18um CMOS technology, shows a SFDR of 49.4dB at the output signal of 551MHz. The prototype DAC consumes 6mW for a Nyquist sinusoidal output signal at a sampling rate of 1.25GHz with the supply voltage of 1.8V. The active area of the chip is 0.0576mm
²
.