Effects of layout methods of RFCMOS on noise performance

This paper presents a study on the effects of different layout methods on the noise performance of RF CMOS transistors. The optimization of RF characteristics using multifinger layout and a more compact waffle layout with Manhattan-oriented polysilicon gate are studied. The waffle layout is demonstrated to have a larger design window through the simulation as well as the experimental data. The improvement of both the maximum oscillation frequency f/sub max/ and the cutoff frequency f/sub T/ at the same biasing condition leads to the improvement on RF noise performance for the waffle MOSFETs. Compared with the multifinger devices, the SpectreRF simulation reveals that 10% reduction in noise figure is achieved when the waffle MOSFETs are used in CMOS low-noise amplifiers.