Thermo-electric characterization of APCVD PolySi/sub 0.7/Ge/sub 0.3/ for IC-compatible fabrication of integrated lateral Peltier elements

The performance of poly-Si/sub 0.7/Ge/sub 0.3/ as a thermo-electric material that is process compatible with IC fabrication in silicon has been analyzed and fully characterized using on-chip MEMS-based test structures. The application is in on-chip thermal stabilization of a micromachined platform in silicon containing a reference component. A CMOS process has been adapted to include SiGe thermo-electric elements. The results are a Seebeck coefficient /spl alpha//sub n/=-179 /spl mu/V/K and /spl alpha//sub p/=131 /spl mu/V/K at 295 K with a TC of 0.2 /spl mu/V/K/sup 2/, and -0.1 /spl mu/V/K/sup 2/, respectively. High-dose implantation and appropriate anneal have been used to achieve an electrical resistivity of 28.9 /spl mu//spl Omega//spl middot/m for p-doped material and 29.2 /spl mu//spl Omega//spl middot/m for n-doped material. Thermal conductivity was measured /spl lambda/=5 Wm/sup -1//spl middot/K/sup -1/, which is close to the theoretical minimum. The contact resistance is identified as an important performance limiting parameter. The resulting figure of merit z/sub dev/=168/spl times/10/sup -6/K/sup -1/, which would enable a temperature difference for Peltier cooling of /spl Delta/T/sub max/=7.3 K. Parasitic thermal conductance limits /spl Delta/T/sub max/ to 2.1 K in this work. Peltier heating and cooling offers superior dynamic performance of temperature control close to ambient temperature, as compared to passive cooling. A response time /spl tau/=2 ms has been found.